RFIC System Engineer – Wireless SoC (CMOS)

Apple, Inc.; San Francisco (CA); On-site; USD 129,000 - 225,000; Full time

Job summary

Apple, Inc. in the San Francisco Bay Area is seeking an experienced RF/analog and mixed-signal design engineer to help deliver state‑of‑the‑art wireless radios in advanced CMOS process nodes.

You will contribute from specification to prototype, collaborating with RF/Analog, Systems/PLL, and FW/SW teams to ensure performance and reliability across high-volume production. The role emphasizes models, tape-out readiness, and close interaction with design and validation teams.

Qualifications

• Minimum requirement of a bachelor's degree.
• RF/analog and mixed signal design experience in RF CMOS design.
• Experience with MATLAB, python , SystemVue or other system level modeling

Responsibilities

• Translate chip or transceiver‑level specifications into detailed block‑level specifications.
• Work with the design and algorithms team to develop models for the impact of analog impairments on transceiver performance.
• Work with the design engineers to ensure block performance meets system requirements through bottom up modeling.
• Overseeing the test and characterization of the design, and debugging issues that may arise from early development stages through productization.
• Working with the technology team to understand the capabilities and limits of the technology node to achieve the optimum performance.

Skills

RF design

Analog design

Mixed-signal design

RF CMOS

MATLAB

Python

SystemVue

Education

Bachelor's degree

Tools

MATLAB

Python

SystemVue

Verilog-A

Job description

Apple, Inc. in the San Francisco Bay Area is seeking an experienced RF/analog and mixed-signal design engineer to help deliver state‑of‑the‑art wireless radios in advanced CMOS process nodes.

You will contribute from specification to prototype, collaborating with RF/Analog, Systems/PLL, and FW/SW teams to ensure performance and reliability across high-volume production. The role emphasizes models, tape-out readiness, and close interaction with design and validation teams.