Remote Semiconductor PDK Testsite Engineer

Computer Task; United States; A distancia; USD 99.000 - 102.000; Jornada completa

Descripción de la vacante

CTG, a Cegeka company, seeks a remote IC design engineer to design testsites, testchips, and PDK components, and to verify layouts using Cadence Virtuoso. The role emphasizes process technology characterization and silicon validation.

You will translate technology specs into silicon-ready layouts, perform DRC/LVS checks, and automate related workflows while collaborating with cross-functional teams. Strong English communication is required.

Formación

• Experience designing test structures and test sites for semiconductor processes.
• Strong knowledge of Cadence Virtuoso and layout verification.
• Familiarity with DRC/LVS and PDK validation processes.

Responsabilidades

• Design and develop semiconductor testsites, testchips, and device structures.
• Create physical layouts using Cadence Virtuoso or similar EDA tools.
• Translate specifications into test structures and silicon-ready layouts.
• Interpret design rules, ground rules, and layout specs.
• Perform and debug DRC/LVS and other physical verifications.
• Automate testsite generation, layout, verification, and data-processing workflows.
• Document testsite designs, verification methodologies, results, and findings.
• Collaborate with process development, device modeling, design enablement, layout, CAD/EDA, test, and manufacturing teams.

Conocimientos

Cadence Virtuoso

IC design and layout

DRC LVS

PDK development

PCells

Python scripting

Tcl scripting

Documentation

Cross-functional communication

Semiconductor devices knowledge

Educación

Bachelor's degree in Electrical Engineering, Computer Engineering, Microelectronics, Physics, or related technical discipline

Herramientas

Synopsys IC Validator (ICV)

Siemens Calibre

SKILL scripting

Python scripting

Tcl scripting

Descripción del empleo

CTG, a Cegeka company, seeks a remote IC design engineer to design testsites, testchips, and PDK components, and to verify layouts using Cadence Virtuoso. The role emphasizes process technology characterization and silicon validation.

You will translate technology specs into silicon-ready layouts, perform DRC/LVS checks, and automate related workflows while collaborating with cross-functional teams. Strong English communication is required.