Remote PDK Testsite Engineer – Cadence Virtuoso

Computer Task Group, Inc; Oregon; Hybrid; USD 99,000 - 102,000; Full time

Job summary

CTG is seeking a PDK Testsite Engineer to design semiconductor testsites and testchips for process characterization. You will create layouts using Cadence Virtuoso, translate specs into silicon-ready structures, and verify designs through DRC/LVS and related checks.

The role involves developing PDK components, documenting methods and results, and collaborating with process development and CAD/EDA teams in a remote, six-month engagement.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• Experience with Cadence Virtuoso and IC design/PDK development.
• Knowledge of DRC/LVS and physical verification.
• Experience with PDK development or validation.
• Strong scripting in Python or Tcl for automation.

Responsibilities

• Design and develop semiconductor testsites, testchips, and device-level structures.
• Create physical layouts using Cadence Virtuoso or similar EDA tools.
• Translate process characterization requirements into test structures and layouts.
• Interpret semiconductor design rules, ground rules, and layout specs.
• Perform and debug DRC/LVS and physical verification.

Skills

Analytical thinking

Cross-functional work

Problem solving

Technical writing

Debugging

Education

Bachelor's degree in Electrical Engineering

Tools

Cadence Virtuoso

IC Validator

Calibre

Python

Tcl

PCells

Job description

CTG is seeking a PDK Testsite Engineer to design semiconductor testsites and testchips for process characterization. You will create layouts using Cadence Virtuoso, translate specs into silicon-ready structures, and verify designs through DRC/LVS and related checks.

The role involves developing PDK components, documenting methods and results, and collaborating with process development and CAD/EDA teams in a remote, six-month engagement.