Remote Principal FPGA/ASIC Design Engineer

Rolls-Royce Corporation; United States; Remote; USD 150,000 - 210,000; Full time

Benefits offered by this job

Total Rewards package including bonus

401(k) retirement savings plan

Paid Time Off

Job summary

Rolls-Royce is seeking a Principal Engineer - FPGA/ASIC Design to join the global electronic engine control team. You will design, verify, integrate and test FPGA/ASIC solutions for current and future engine control units, with up to 25% travel.

This role requires hands-on RTL development and documentation for certification. Responsibilities include timing closure, DO-254 verification, and use of Xilinx/Actel tool flows; strong lab debugging with ILA/JTAG; collaboration across disciplines.

Qualifications

• Bachelor's degree in Electronics or Computer Engineering with 5+ years of experience.
• Master's degree with 3+ years or PhD in Electronics/Computer Engineering.
• U.S. Citizen required to be eligible for role.

Responsibilities

• Participate in all project phases to produce design documentation, verification plans and reports.
• Design and develop ASIC/FPGA to support RR engine control units.
• Verify complex FPGA/ASIC designs for DO-254 compliance.
• Develop RTL using VHDL/Verilog/SystemVerilog and debug via simulations.
• Achieve timing closure on FPGA designs and generate test benches.
• Evaluate design flow from high-level design to place-and-route, timing, and power use.

Skills

FPGA/ASIC design expertise

Scripting (TCL, Python, Shell)

Windows & Linux development

Version control (Git, SVN)

SysML modeling tools (Cameo/SysML)

Model-based systems engineering (MATLA

VHDL/Verilog/SystemVerilog

Education

Bachelor's degree in Electronics or Computer Engineering

Master's degree in Electronics or Computer Engineering

PhD in Electronics or Computer Engineering

Tools

Actel tool flows

Xilinx tool flows

ILA/JTAG test equipment

Job description

Rolls-Royce is seeking a Principal Engineer - FPGA/ASIC Design to join the global electronic engine control team. You will design, verify, integrate and test FPGA/ASIC solutions for current and future engine control units, with up to 25% travel.

This role requires hands-on RTL development and documentation for certification. Responsibilities include timing closure, DO-254 verification, and use of Xilinx/Actel tool flows; strong lab debugging with ILA/JTAG; collaboration across disciplines.