Principal FPGA/ASIC Design Engineer - Hybrid

Rolls-Royce; Washington (District of Columbia); Hybrid; USD 152,000 - 247,000; Full time

Benefits offered by this job

Hybrid work schedule

Discretionary bonus plan

Comprehensive benefits

Job summary

Rolls-Royce is seeking a Principal Engineer for FPGA/ASIC design in Reston, VA, with a hybrid schedule (3 office days/week) and up to 25% travel to sites in Indianapolis and West Lafayette, IN. You will design, verify, integrate, and test FPGA/ASIC solutions for RR engine control units.

The role emphasizes RTL development in VHDL/Verilog/SystemVerilog, verification, and DO-254 compliant practice, with collaboration across a global multi-disciplinary team. A US citizenship is required.

Qualifications

• Bachelor’s degree in Electronics Engineering and/or Computer Engineering with 5+ years of experience, OR
• Master’s degree in Electronics Engineering and/or Computer Engineering with 3+ years of experience, OR
• PhD in Electronics Engineering and/or Computer Engineering

Responsibilities

• Design, verify, integrate, and test FPGA/ASIC solutions for Rolls-Royce engine control systems.
• Develop RTL using VHDL/Verilog/SystemVerilog and create test benches.
• Verify complex FPGA/ASIC products to DO-254 standards.
• Evaluate flow: design, synthesis, place-and-route, timing, and power.

Skills

FPGA design

ASIC design

RTL design

VHDL/Verilog/SystemVerilog

RTL languages

Education

Bachelor’s degree in Electronics/Computer Engineering

Master’s degree in Electronics/Computer Engineering

PhD in Electronics/Computer Engineering

Tools

Git

SVN

Xilinx tool flow

Actel tool flows

Cameo Systems Modeler

MATLAB/Simulink

TCL scripting

Python scripting

Job description

Rolls-Royce is seeking a Principal Engineer for FPGA/ASIC design in Reston, VA, with a hybrid schedule (3 office days/week) and up to 25% travel to sites in Indianapolis and West Lafayette, IN. You will design, verify, integrate, and test FPGA/ASIC solutions for RR engine control units.

The role emphasizes RTL development in VHDL/Verilog/SystemVerilog, verification, and DO-254 compliant practice, with collaboration across a global multi-disciplinary team. A US citizenship is required.