Principal FPGA/ASIC Design Engineer — Hybrid (Indy/Reston)

Rolls-Royce; Indianapolis (IN); Hybrid; USD 140,000 - 240,000; Full time

Benefits offered by this job

Hybrid work schedule

Relocation assistance

Discretionary bonus plan

Competitive benefits

Job summary

Rolls-Royce is seeking a Principal Engineer for FPGA/ASIC design to drive development of digital hardware for engine control units. The role requires hands-on RTL design using VHDL/Verilog/SystemVerilog, verification and timing closure, and integration across multiple sites.

The position supports hybrid work in Indianapolis, IN or Reston, VA, with up to 25% travel. A strong background in FPGA/ASIC design and DO-254 is essential, along with US citizenship.

Qualifications

• Bachelor’s degree in Electronics/Computer Engineering with 5+ years of FPGA/ASIC experience
• U.S. Citizenship is required for this role
• Experience verifying FPGA/ASIC designs to DO-254
• Strong RTL experience with VHDL/Verilog/SystemVerilog

Responsibilities

• Produce detailed design documentation, verification plans and reports
• Design and develop custom digital devices (ASIC/FPGA) for RR engine control units
• Verify FPGA/ASIC products to DO-254 requirements
• Develop RTL using VHDL/Verilog/SystemVerilog and run simulations
• Achieve timing closure on FPGA designs and generate test benches
• Evaluate design flow including synthesis, place-and-route, timing and power constraints

Skills

FPGA/ASIC design

RTL design

Verilog

VHDL

SystemVerilog

DO-254

Scripting (TCL/Python)

Windows/Linux

Git/SVN

Xilinx/Actel tools

MATLAB/Simulink

SysML modelling

Education

Bachelor’s degree in Electronics/Computer Engineering

Master’s degree in Electronics/Computer Engineering

PhD in Electronics/Computer Engineering

Tools

Xilinx tool flows

Actel tool flows

Simulink MATLAB

CAMEO Systems Modeler

Job description

Rolls-Royce is seeking a Principal Engineer for FPGA/ASIC design to drive development of digital hardware for engine control units. The role requires hands-on RTL design using VHDL/Verilog/SystemVerilog, verification and timing closure, and integration across multiple sites.

The position supports hybrid work in Indianapolis, IN or Reston, VA, with up to 25% travel. A strong background in FPGA/ASIC design and DO-254 is essential, along with US citizenship.