Hybrid Principal FPGA/ASIC Design Engineer

rollsroyce; Indianapolis (IN); Hybrid; USD 150,000 - 210,000; Full time

Job summary

Rolls-Royce is hiring a Principal Engineer for FPGA/ASIC design to develop, verify, and test digital solutions for their engine control systems. The role involves RTL coding, simulation, and DO-254 compliant verification within a hybrid work model.

Candidates should have 5+ years in electronics design (or a relevant PhD) and be able to travel up to 25% between Indianapolis and other US sites. U.S. citizenship is required.

Qualifications

• Bachelor’s or higher degree in electronics or computer engineering.
• 5+ years of FPGA/ASIC design experience.
• U.S. citizenship is required.

Responsibilities

• Design, verify, integrate FPGA/ASIC solutions for engine control units.
• Develop RTL in VHDL/Verilog/SystemVerilog and run simulations.
• Create test benches and documentation for certification.
• Ensure timing closure and power usage optimization.
• Prepare design verification plans and reports.
• Travel up to 25% between sites as needed.

Skills

RTL design

Timing closure

Simulation

Test benches

Scripting Python

Debug with JTAG/ILA

Education

Bachelor's degree in Electronics or Computer Engineering

Master's degree in Electronics or Computer Engineering

PhD in Electronics or Computer Engineering

Tools

VHDL

Verilog

SystemVerilog

DO-254 verification

Job description

Rolls-Royce is hiring a Principal Engineer for FPGA/ASIC design to develop, verify, and test digital solutions for their engine control systems. The role involves RTL coding, simulation, and DO-254 compliant verification within a hybrid work model.

Candidates should have 5+ years in electronics design (or a relevant PhD) and be able to travel up to 25% between Indianapolis and other US sites. U.S. citizenship is required.