Real-Time FPGA Emulation Architect

Renesas Electronics Corporation; Austin, Northern (TX, KY); Hybrid; USD 170,000 - 230,000; Full time

Job summary

Renesas is seeking a Principal FPGA Emulation & Prototyping Engineer to build and own the FPGA-based platforms that emulate our mixed-signal power ASICs before silicon. Working with RTL and DSP architects, you will validate real-time loops and de-risk tape-out.

You will lead emulation efforts, map designs onto FPGA fabric, integrate analog/power interfaces, and mentor engineers across teams. This is a hands-on role demanding deep FPGA expertise and strong debugging skills.

Qualifications

• Extensive FPGA design and implementation experience (typically 10+ years) involving ASIC/SoC prototyping or emulation.
• Expert-level RTL design in SystemVerilog and/or VHDL with deep ASIC RTL experience.
• Deep understanding of FPGA internal architecture and primitives and how to map designs to meet real-time emulation.
• Hands-on experience adapting ASIC RTL for FPGA: clock-gating conversion, memory macro replacement, resets, and CDC handling.
• Strong command of the full FPGA flow — synthesis, place-and-route, timing analysis, and constraints (XDC/SDC).
• Hardware bring-up, in-system debugging, lab instrumentation, and long pre-silicon debug.
• Proficiency in automation scripting (TCL, Python).
• Demonstrated technical leadership through mentoring and cross-team decisions.

Responsibilities

• Partner closely with silicon RTL and DSP architects to bring ASIC designs up on FPGA, turning architectural intent into a real-time emulation platform.
• Adapt ASIC RTL for FPGA emulation while preserving functional equivalence to the golden design.
• Map designs onto the FPGA fabric to hit emulation speed and manage DSP/memory resources.
• Build the real-time environment around the digital core with analog/power interfaces and hardware-in-the-loop where needed.
• Develop deep pre-silicon debug: waveform capture, triggering, assertions, and co-development workflows.
• Define and improve emulation methodology, flows, and automation across teams.
• Provide technical leadership: mentor engineers, lead reviews, and drive emulation/tooling decisions.

Skills

FPGA design & prototyping

RTL design (SystemVerilog/VHDL)

FPGA implementation flow (Vivado/Quart

Scripting: TCL/Python

Hardware bring-up & debugging

Technical leadership

Embedded firmware exposure (C/C++)

Education

BS/MS in Electrical Engineering or related field

Tools

Vivado / Quartus

In-system debugging (ILA/SignalTap)

HAPS / Protium / Veloce platforms

Xilinx/Intel FPGA devices

Python scripting

Job description

Renesas is seeking a Principal FPGA Emulation & Prototyping Engineer to build and own the FPGA-based platforms that emulate our mixed-signal power ASICs before silicon. Working with RTL and DSP architects, you will validate real-time loops and de-risk tape-out.

You will lead emulation efforts, map designs onto FPGA fabric, integrate analog/power interfaces, and mentor engineers across teams. This is a hands-on role demanding deep FPGA expertise and strong debugging skills.