FPGA Prototyping / Emulation Engineer

Mirafra Technologies; San Francisco (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

Mirafra Technologies seeks an experienced FPGA prototyping/ hardware emulation engineer to design, optimize, and bring up large-scale SoC prototyping flows.

You will adapt ASIC RTL for FPGA platforms, perform timing closure, resource optimization, and debug across multi-FPGA setups, collaborating with RTL, DV, firmware, and software teams.

Qualifications

• 5+ years of hands-on experience in FPGA prototyping and/or hardware emulation.
• Strong knowledge of Verilog/SystemVerilog and digital design fundamentals.
• Experience with FPGA synthesis, implementation, timing constraints, and timing closure.
• Hands-on experience with Vivado, Quartus, Synplify, or equivalent tools.
• Experience with HAPS, ZeBu, Palladium, Protium, or Veloce is highly preferred.
• Strong debugging skills using waveform/debug tools and FPGA instrumentation.
• Proficiency in Python/TCL/Perl/Shell scripting.
• Good understanding of SoC architecture, clock/reset domains, and standard interfaces such as AXI/AMBA, PCIe, DDR, USB, CXL, or similar.
• Experience with C/C++/SystemC, UVM, or firmware/software bring-up is a plus.
• Strong analytical, communication, and problem-solving skills.

Responsibilities

• Develop and support FPGA prototyping and emulation flows for large-scale SoCs.
• Convert and adapt ASIC RTL for FPGA implementation, including partitioning, synthesis, timing closure, and resource optimization.
• Work with platforms such as HAPS/ZeBu, Protium/Palladium, or Veloce.
• Perform prototype bring-up, RTL debug, hardware debug, and performance optimization.
• Enable pre-silicon software/firmware bring-up and HW/SW co-validation.
• Debug issues involving clocks, resets, memories, interfaces, timing, and multi-FPGA communication.
• Develop automation and infrastructure using Python, TCL, Perl, or Shell scripting.
• Collaborate with RTL, DV, architecture, firmware, and software teams to resolve complex issues.
• Analyze FPGA resource utilization, timing, compilation, and runtime performance.
• Support regression, validation, documentation, and development of reusable prototyping methodologies.

Skills

FPGA prototyping

Hardware emulation

Verilog/SystemVerilog

FPGA synthesis

Timing closure

Vivado

Quartus

Synplify

HAPS

ZeBu

Palladium

Protium

Veloce

Python scripting

TCL scripting

Perl scripting

Shell scripting

SoC architecture

AXI/AMBA interfaces

PCIe

DDR

CXL

C/C++/SystemC

UVM

Firmware bring-up

Tools

Vivado

Quartus

Synplify

Job description

Develop and support FPGA prototyping and emulation flows for large-scale SoCs.

Convert and adapt ASIC RTL for FPGA implementation, including partitioning, synthesis, timing closure, and resource optimization.

Work with platforms such as Synopsys HAPS/ZeBu, Cadence Protium/Palladium, or Siemens Veloce.

Perform prototype bring-up, RTL debug, hardware debug, and performance optimization.

Enable pre-silicon software/firmware bring-up and HW/SW co-validation.

Debug issues involving clocks, resets, memories, interfaces, timing, and multi-FPGA communication.

Develop automation and infrastructure using Python, TCL, Perl, or Shell scripting.

Collaborate with RTL, DV, architecture, firmware, and software teams to resolve complex issues.

Analyze FPGA resource utilization, timing, compilation, and runtime performance.

Support regression, validation, documentation, and development of reusable prototyping methodologies.

Required Skills

5+ years of hands-on experience in FPGA prototyping and/or hardware emulation.

Strong knowledge of Verilog/SystemVerilog and digital design fundamentals.

Experience with FPGA synthesis, implementation, timing constraints, and timing closure.

Hands-on experience with Vivado, Quartus, Synplify, or equivalent tools.

Experience with HAPS, ZeBu, Palladium, Protium, or Veloce is highly preferred.

Strong debugging skills using waveform/debug tools and FPGA instrumentation.

Proficiency in Python/TCL/Perl/Shell scripting.

Good understanding of SoC architecture, clock/reset domains, and standard interfaces such as AXI/AMBA, PCIe, DDR, USB, CXL, or similar.

Experience with C/C++/SystemC, UVM, or firmware/software bring-up is a plus.

Strong analytical, communication, and problem-solving skills.