R&D IC Design Engineer

Broadcom; Irvine (CA); On-site; USD 140,000 - 200,000; Full time

Benefits offered by this job

Equity grant

Discretionary annual bonus

401(k) matching

Health insurance

Job summary

Broadcom in Irvine, CA is seeking a senior ASIC design engineer to architect block level designs for high-speed optical communication transceivers. You will translate marketing requirements into detailed designs, manage timing, and oversee RTL coding, synthesis, and validation.

You should have a strong background in ARM subsystems, high-speed digital circuits, RTL languages (Verilog/VHDL), and scripting (Python/Unix). Extensive collaboration across remote teams is expected.

Qualifications

• B.S. in EE or CE; minimum 8 years related experience.
• M.S./Ph.D. in EE/CE with 6+ years preferred.
• Strong knowledge of ARM subsystems.
• Expertise in high-speed digital circuit design and Ethernet/OTN familiarity.
• Experience with FEC and DSP concepts is a plus.
• Hands-on lab debugging and design-for-test experience.
• Proficiency in RTL simulation, synthesis and timing closure.

Responsibilities

• Architect block-level design from marketing/system requirements.
• Prepare design documents and timing constraints.
• RTL coding, lint, CDC, synthesis, and RTL/gate-level simulations.
• Perform design tradeoffs for leakage, power and area.
• Silicon bring-up, ATE program support, and validation.
• Develop verification and test plans for design validation.

Skills

ARM subsystem

high speed digital design

RTL design

RTL simulation

Scripting/Python/Unix

Verilog

VHDL

C

Synthesis/Timing

Power/TPD design

Education

B.S in EE or Computer Engineering

M.S or Ph.D in EE/CE

Tools

Verilog

VHDL

Unix/Perl/Python

Job description

Job Description:

This opening is for working on chips that enable Physical Layer Products for High

Job Description:

This opening is for working on chips that enable Physical Layer Products for High

Speed Optical Communication.

architect block level design specifications from the marketing requirements and/or

system requirements

prepare detailed design document, timing constraint file

RTL coding, Lint checks, CDC, Synthesis, Equivalency checking, STA, RTL/gate level

simulations & silicon debug

Scripting for various IC design tasks such as STA, equivalency checks, test bench,

simulations, synthesis, etc.

prepare block level resource requirements & development schedule

generate verification & test plans for design validation

Perform design tradeoff analysis – leakage, dynamic power, die size, schedule, resource, priority, etc.

silicon bring up and validation, ATE program bring up

Job Requirement:

B.S degree in EE or computer Engineering. Minimum of 8 years of work experience with

direct related technical skill

M.S degree/Ph.D in EE or Computer Engineering with 6 years of work experience.

Good knowledge of ARM subsystem

Good knowledge of high speed digital circuit design.

Good knowledge of digital upsampling/downsampling

Good knowledge of 10G/100G/200G/400G/800G Ethernet and OTN network.

Good knowledge on FEC (Forward Error Correction) design.

Good knowledge of digital signal processing and error correction code is a plus

Strong analytical and problem solving skills as well as hands-on lab debugging

experiences

Good knowledge of RTL simulation and synthesis.

In-depth knowledge for design for low power and design for test and design for

manufacturing.

Good Knowledge in languages relevant to the ASIC development process including

Verilog, VHDL, Unix/Perl Scripting or Python, and C.

Self-motivated, excellent communication skills and ability to excel in a team

environment.

Good organization skills, able to follow through & bring issue to closure

Understand the entire IC development flow & procedure including silicon volume

production qualification requirements & procedures

Enthusiastic & enjoy IC development works

Be able to work with teams at remote locations with different time zone.

Compensation And Benefits

The annual base salary range for this position is To

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

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