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Broadcom seeks an experienced RTL design engineer to conceive and develop leadership silicon for AI/ML and cloud data centers, with a strong focus on front-end design and Si debugging.
Candidates should have 18+ years in RTL design (BSEE) or 16+ years with an MSEE and Python/Perl experience, plus excellent communication and teamwork abilities. Irvine, CA-based role with a competitive package.
Would you like to conceive and develop leadership silicon technology for leading AI/ML and cloud operators? Come join the team creating technology that fuels the next generation AI/ML networks, mobile content, and cloud mega data centers!
Would you like to conceive and develop leadership silicon technology for leading AI/ML and cloud operators? Come join the team creating technology that fuels the next generation AI/ML networks, mobile content, and cloud mega data centers!
The candidate will work on leading edge products in the area of Ethernet/IP switching for multi-scale data centers. We are looking for engineers that are detail oriented and are capable of designing complex IP blocks in an accelerated schedule.
This is a rare opportunity to be part of a team that leads products for a new line of devices. The candidate will work with our worldwide design and architecture teams to develop leading edge products.
All aspects of front end design will be involved, with strong emphasis on design / Si debug.
BSEE and 18+ years of industry experience in RTL design is a must, or MSEE and 16 experience using Python / Perl is a plus
Must have strong communication and documentation skills. Must be a self-starter and a strong team player.
The annual base salary range for this position is USD 150,800.00 To USD 241,200.00
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
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