Process Integration Engineer — Yield & CD Optimization

Intel; Phoenix (AZ); On-site; USD 104,000 - 199,000; Full time

Benefits offered by this job

Stock bonuses

Health insurance

Retirement plan

Paid time off

Job summary

Intel in the United States seeks an experienced engineer to develop and define integrated front end process flows for new technology nodes. You will coordinate with lithography, etch, deposition, diffusion, wet cleaning, CMP, and metrology teams to establish robust process windows and integration schemes.

The role emphasizes yield improvement, device performance optimization, and statistical process control from R&D to high-volume manufacturing.

Qualifications

• PhD in Electrical Engineering, Physics, Applied Physics, Optics, Material Science, Chemical Engineering, Mechanical Engineering, or related discipline.
• 6+ months experience in semiconductor device fabrication, electrical characterization of transistors or devices, or clean room process development.
• Preferred: strong understanding of device physics (CMOS, FinFET, GAA) and hands-on VLSI fabrication/testing knowledge.
• Familiarity with JMP, MATLAB, scripting languages (Python, JSL, TCL) or programming languages (SQL, C/C++).

Responsibilities

• Develop and define integrated front end process flows for new technology nodes.
• Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, and metrology teams.
• Establish process windows and integration schemes to improve yield and parametric performance.
• Analyze yield loss and perform root cause analysis using SPC, DOE, FMEA.

Skills

JMP

MATLAB

Python

JSL

TCL

SQL

C/C++

Education

PhD in Electrical Engineering, Physics, Applied Physics, Optics, Material Science, Chemical Engineering, Mechanical Engineering, or related discipline

Tools

JMP

MATLAB

Python

JSL

TCL

SQL

C/C++

Job description

Intel in the United States seeks an experienced engineer to develop and define integrated front end process flows for new technology nodes. You will coordinate with lithography, etch, deposition, diffusion, wet cleaning, CMP, and metrology teams to establish robust process windows and integration schemes.

The role emphasizes yield improvement, device performance optimization, and statistical process control from R&D to high-volume manufacturing.