Principal ATE Test Engineer

Asteralabs; San Jose (CA); On-site; USD 209,000 - 230,000; Full time

Job summary

Asteralabs is seeking a Principal Test Engineer in San Jose, California to lead ATE test solutions for complex mixed-signal silicon SoC products. This role involves developing SoC test strategies, engaging with manufacturing partners, and defining ATE programs throughout the production process.

The ideal candidate will have a strong technical background with at least 8 years of experience in high-speed mixed-signal testing and substantial programming skills. Asteralabs values diverse ideas and encourages candidates from various backgrounds to apply.

Qualifications

• At least 8 years of experience releasing complex SoC/silicon products.
• Proficient in data processing using high-level programming languages.
• Hands-on experience with high-speed mixed-signal SoC test on multiple platforms.

Responsibilities

• Develop and oversee SoC test strategy.
• Interact with manufacturing partners to define ATE programs.
• Optimize tester resources while maintaining product quality.

Skills

High-speed mixed signal SoC test program development

ATE programming

I2C communication

C/C++ programming

Strong team collaboration

Education

Bachelor’s degree in Electrical Engineering

Master’s degree in Electrical Engineering

Tools

Advantest 93k ATE platform

Protocol analyzers

Oscilloscopes

Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Job Description

We are looking for Principal Test Engineers with proven experience in developing and supporting complex mixed-signal silicon SoC products to lead ATE Test solutions. The ideal candidate will develop and oversee SoC test strategy, interact with manufacturing partners, define and implement ATE programs, and own the product from design and initial samples all the way through high volume production ramp. The candidate should have working knowledge of communication/interface protocols such as PCI-Express (Gen-4/5/6), Ethernet, Infiniband, DDR, NVMe, USB, etc.

Basic Qualifications

• Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Master’s is preferred.
• ≥8-year experience releasing complex SoC/silicon products to high volume manufacturing.
• Working knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc.
• Professional attitude with ability to execute on multiple tasks with minimal supervision.
• Strong team player with good communication skills to work alongside a team of high caliber engineers.
• Entrepreneurial, open-mind behavior and can-do attitude.

Required Experience

• Hands‑on experience with high-speed mixed signal SoC test program/hardware development on multiple high-speed test platforms.
• Collaboration with design team to define test strategy, create and own test plan.
• Tester platform selection, design, and development of ATE hardware for wafer sort and final test.
• Familiar with high-speed load board design techniques.
• Proven track record of implementing ATE patterns to optimize tester resources and minimize ATE test time while maintaining product quality.
• Strong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage – SCAN, MEMBIST, SerDes and other functional tests.
• Skilled in control interfaces – I2C, I3C, SPI, MDIO, JTAG etc.
• Expertise in production test of high‑speed SerDes operating at 16Gbps and higher.
• Skilled in ATE programming, silicon/ATE bring‑up, bench‑ATE correlation and debug.
• Experience with lab equipment including protocol analyzers and oscilloscopes.
• Experience with using Advantest 93k ATE platform.
• Proficiency in, at least, one modern programming language such as C/C++, Python.

Preferred Experience

• Fluent in data processing using high level programming languages.
• Experience in running External loopback at wafer sort.
• Familiarity with modern databases.

The base salary range is $209,000.00 USD – $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non‑binary people, veterans, parents, and individuals with disabilities.