Principal ATE Test Engineer

Astera Labs; Santa Clara (CA); On-site; USD 209,000 - 240,000; Full time

Job summary

Astera Labs is seeking a Principal ATE Test Engineer in Santa Clara, CA to lead ATE solutions for mixed-signal SoCs. You will define and drive test strategy, collaborate with manufacturing partners, and own the product from design through ramp to high-volume production.

Candidates need hands-on, multi-project dedication and strong knowledge of high-speed protocols. The role demands expanding DFT techniques, wafer sort and final test, and experience with Teradyne/Advantest 93k platforms, along

Qualifications

• Bachelor's in Electrical Engineering required; Master’s preferred.
• ≥8 years releasing complex SoC/silicon products to high-volume manufacturing.
• Experience with high-speed protocols (PCIe, Ethernet, Infiniband, DDR, NVMe, USB).
• Ability to manage multiple tasks with minimal supervision.
• Strong team player with excellent communication.
• Entrepreneurial, open-minded, can-do attitude.

Responsibilities

• Develop and oversee SoC test strategy for mixed-signal silicon.
• Interact with manufacturing partners to define and implement ATE programs.
• Own the product from design through high-volume production ramp.
• Lead test platform selection and ATE hardware development for wafer sort and final test.
• Collaborate with design team to define test strategies and test plans.
• DFT optimization and parallel testing to maximize coverage.

Skills

Electrical engineering

Test engineering

Team collaboration

Multi-tasking

Communication

Entrepreneurial mindset

Education

Bachelor's in EE

Master's in EE (preferred)

Tools

Teradyne 93k ATE

Advantest 93k ATE

Oscilloscopes

Protocol Analyzers

Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .

Job Description

We are looking for Principal ATE Test Engineers with proven experience in developing and supporting complex mixed-signal silicon SoC products to lead ATE Test solutions. The ideal candidate will develop and oversee SoC test strategy, interact with manufacturing partners, define, and implement ATE programs and own the product from design, initial samples all the way through high volume production ramp. The candidate should have working knowledge of communication/interface protocols such as PCI-Express (Gen-4/5/6), Ethernet, Infiniband, DDR, NVMe, USB, etc.

Basic Qualifications

• Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Master’s is preferred.
• ≥8-year experience releasing complex SoC/silicon products to high volume manufacturing.
• Working knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc.
• Professional attitude with ability to execute on multiple tasks with minimal supervision.
• Strong team player with good communication skills to work alongside a team of high caliber engineers.
• Entrepreneurial, open-mind behavior and can-do attitude.

Required Experience

• Hands-on experience with high-speed mixed signal SoC test program/hardware development on multiple high-speed test platforms.
• Collaboration with design team to define test strategy, create and own test plan.
• Tester platform selection, design, and development of ATE hardware for wafer sort and final test.
• Familiar with high-speed load board design techniques.
• Proven track record of implementing ATE patterns to optimize tester resources and minimize ATE test time while maintaining product quality.
• Strong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage – SCAN, MEMBIST, SerDes and other functional tests.
• Skilled in control interfaces – I2C, I3C, SPI, MDIO, JTAG etc.
• Expertise in production test of high speed SerDes operating at 16Gbps and higher.
• Skilled in ATE programming, silicon/ATE bring-up, bench-ATE correlation and debug.
• Experience with lab equipment including protocol analyzers and oscilloscopes.
• Experience with using Teradyne or Advantest 93k ATE platform.
• Proficiency in, at least, one modern programming language such as C/C++, Python.

Preferred Experience

• Fluent in data processing using high level programming languages.
• Experience in running External loopback at wafer sort.
• Familiarity with modern databases
• Basic knowledge of RF Testing on ATE Platform.

The base salary range is $209,000.00 USD – $240,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.