Principal Technology Development Engineer

Silicon Desert Staffing

Bloomington (IN)

On-site

USD 120,000 - 180,000

Full time

4 days ago
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Benefits offered by this job

Competitive salaries
Relocation & sign on bonus
Annual bonus plan
401(k) match
Ample PTO
Medical/dental/vision
Accident & critical illness insurance
On-site gym
Tuition reimbursement
Employee recognition programs

Job summary

Silicon Desert Staffing seeks a senior front-end process engineer to develop FEOL steps for CMOS, BCDMOS, and power devices. You will design process flows, run TCAD simulations, and build/ analyze experiments to meet manufacturability and performance targets.

You’ll support early test‑chip builds, debug issues, define layout rules, and plan mask sets. A graduate degree and 5+ years in the field are required; a hands‑on, cross‑functional role awaits.

Qualifications

  • 5+ years of relevant experience.
  • Graduate degree (MS or PhD) in Electrical Engineering, Physics, Materials Science, or a related field.
  • Strong understanding of all FEOL process modules (silicon, epitaxy, diffusion, etch, lithography, thin films).
  • Experience in process integration for CMOS, BCDMOS, or discrete power devices.
  • Solid foundation in semiconductor device physics.
  • Ability to design process flows to meet manufacturability and electrical performance targets.
  • Experience correlating electrical test results with process and cross‑sectional data.
  • Familiarity with failure analysis methodologies and interpretation of FA results.
  • Understanding of power‑device packaging, assembly, and reliability considerations.
  • Experience with backend processes (e.g., BGBM, STM).
  • Proficiency in DoE methodologies and data analysis tools (e.g., JMP, Spotfire).
  • Experience with TCAD simulations and layout interpretation.
  • Strong cross‑functional communication skills and ability to drive technical solutions.

Responsibilities

  • Develop and improve front-end semiconductor process steps used to build advanced CMOS, BCD, and power devices.
  • Design FEOL process flows and run TCAD simulations.
  • Build and analyze experiments to optimize manufacturability, electrical performance, and reliability.
  • Work with cross‑functional teams to optimize modules for manufacturability and reliability.
  • Support early test‑chip builds, debug issues, define layout rules, and help plan mask sets.
  • Hands‑on, technical process‑integration role from concept through early silicon.

Skills

FEOL process know-how
Device physics
Cross-functional collaboration
Process integration
DOE methods

Education

MS or PhD in EE, Physics, Materials Science or related field

Tools

TCAD simulations
JMP
Spotfire

Job description

This role develops and improves the front‑end semiconductor process steps used to build advanced CMOS, BCD, and power devices. You’ll design FEOL process flows, run TCAD simulations, build and analyze experiments, and work with cross‑functional teams to optimize modules for manufacturability, electrical performance, and reliability. You’ll support early test‑chip builds, debug issues, define layout rules, and help plan mask sets. It’s a hands‑on, technical process‑integration role focused on enabling new technologies from concept through early silicon.

  • 5+ years of relevant experience.
  • Graduate degree (MS or PhD) in Electrical Engineering, Physics, Materials Science, or a related field
  • Strong understanding of all FEOL process modules (silicon, epitaxy, diffusion, etch, lithography, thin films).
  • Experience in process integration for CMOS, BCDMOS, or discrete power devices.
  • Solid foundation in semiconductor device physics.
  • Ability to design process flows to meet manufacturability and electrical performance targets.
  • Experience correlating electrical test results with process and cross‑sectional data.
  • Familiarity with failure analysis methodologies and interpretation of FA results.
  • Understanding of power‑device packaging, assembly, and reliability considerations.
  • Experience with backend processes (e.g., BGBM, STM).
  • Proficiency in DoE methodologies and data analysis tools (e.g., JMP, Spotfire).
  • Experience with TCAD simulations and layout interpretation.
  • Strong cross‑functional communication skills and ability to drive technical solutions.
  • competitive salaries
  • relocation & sign on bonus
  • annual bonus plan
  • 401(k) match
  • ample PTO
  • medical/dental/vision
  • accident & critical illness insurance
  • on-site gym
  • tuition reimbursement
  • employee recognition programs
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