Principal System Power & Performance Architect - Datacenter

NVIDIA Corporation (old); Santa Clara (CA); Hybrid; USD 232,000 - 368,000; Full time

Benefits offered by this job

Equity

Comprehensive benefits package

Job summary

NVIDIA Corporation seeks a Principal System Power Management and Performance Architect to own and drive system-level power and performance across multi-IP platforms. You will shape boot flows, low-power entry/exit, and platform state coordination for datacenter-scale workloads.

This role demands 15+ years of architecture experience, deep knowledge of HSIO, DVFS, and P-states, and a proven record turning ambiguity into scalable architecture across silicon generations.

Qualifications

• BS or MS in EE/CE, or equivalent experience proven through the work itself.
• 15+ years of system architecture, development, and validation experience with power and performance-per-watt optimization in datacenter or high-performance platforms.
• Experience guiding architecture decisions across silicon programs and demonstrated case-based reasoning from first principles.

Responsibilities

• Define the multi-generation roadmap for system-level power and performance features.
• Own the architecture and integration strategy for HSIO power management, DVFS, P-states, and low-power features.
• Lead system-level boot and IST architecture across complex multi-IP systems.
• Drive power management strategy at datacenter scale, including rack-level telemetry and platform state coordination.

Skills

System power management

DVFS

P-states

HSIO power management

Power-performance optimization

Datacenter power telemetry

Education

BS or MS in EE/CE

Job description

NVIDIA Corporation seeks a Principal System Power Management and Performance Architect to own and drive system-level power and performance across multi-IP platforms. You will shape boot flows, low-power entry/exit, and platform state coordination for datacenter-scale workloads.

This role demands 15+ years of architecture experience, deep knowledge of HSIO, DVFS, and P-states, and a proven record turning ambiguity into scalable architecture across silicon generations.