Principal Software Engineer - Compiler Development

Cadence; New Jersey; On-site; USD 118,000 - 218,000; Full time

Job summary

Cadence Design Systems is a leader in providing EDA software, hardware, and IP for complex IC design and electronic systems. The Senior Engineer in the System Verification Group will push the capabilities of the Xcelium compiler, tackle multi-billion gate challenges, and drive scalable verification for AI and neural processing units.

Join a team focused on language evolution, high-performance architectures, and rapid innovation in a world of AI-driven silicon design.

Qualifications

• BS with 10+ years, or MS with 7+, or PhD with 5+ years.
• 5+ years in Compiler Development, EDA, or HPC.
• Expert-level C++ (modern standards) and SystemVerilog/Verilog.
• Strong background in compiler theory: lexing, parsing, semantic analysis, code generation.
• Experience with multi-threading, memory management, and cache locality optimizations.

Responsibilities

• Design and implement SystemVerilog language extensions.
• Develop high-performance front-end and code generation components for the compiler.
• Conduct deep-dive bottleneck analyses and optimize C++ code for speed and memory footprint.
• Architect compiler and simulator tuned for complex AI designs and NPUs.
• Explore blue-sky features, including parallel and distributed compilation.

Skills

C++ (modern)

SystemVerilog

Compiler theory

Multi-threading

Memory management

Cache locality

LLVM familiarity

Python

UVM familiarity

Education

BS degree

MS degree

PhD

Tools

LLVM

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence Design Systems is a leading provider of the software, hardware, and intellectual property required to design complex integrated circuits and electronic systems. By offering Electronic Design Automation (EDA) tools, they enable engineers to simulate, verify, and optimize chip designs for various high-growth industries, including automotive, 5G, and hyperscale computing. Beyond software, Cadence provides specialized hardware for emulation and prototyping, alongside a strategy focused on Intelligent System Design that integrates AI and multiphysics analysis to streamline the development of modern electronics. The Xcelium compiler and build performance team develops the compiler and code generator for Xcelium logic simulator. We are developing the next generation compiler capable of verifying highly complex chip designs. Join the team behind Xcelium, the industry-leading logic simulator, to architect the next generation of hardware verification technology. As a Senior Engineer in the System Verification Group, you will be at the forefront of EDA innovation, evolving the SystemVerilog compiler to meet the staggering complexity of future AI and hyperscale chip designs. We are looking for dynamic engineers who thrive on "impossible" scaling challenges and want to invent the algorithms that will power tomorrow’s silicon.

Key Responsibilities

• Language Evolution: Design and implement advanced SystemVerilog language extensions.
• Compiler Architecture: Develop and optimize high-performance front-end and code generation compiler components, focusing on intermediate representations (IR) that scale to multi-billion gate designs.
• Performance Engineering: Conduct deep-dive bottleneck analysis and implement performance optimizations in C/C++ to improve compilation speed and memory footprint.
• Design Scalability: Architect compiler and simulator specifically tuned for complex AI designs, ensuring the engine can handle the massive replicated and parallel structures inherent in next-gen neural processing units (NPUs).
• Innovation & Research: Explore and prototype "blue-sky" features, LLM enhanced Compilation, parallel compilation, distributed compilation.

Qualifications

• BS with a minimum of 10 years of experience OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience
• 5+ years in Compiler Development, EDA, or High-Performance Computing.
• Expert-level C++ (modern standards) and a deep understanding of SystemVerilog or Verilog.
• Proven track record in compiler theory (lexing, parsing, semantic analysis, code generation).
• Experience with multi-threading, memory management, and cache-locality optimizations.

Why This Role is Exciting

"You aren't just maintaining a tool; you are building the backbone of the semiconductor industry. As AI chips grow in complexity, the compiler becomes the primary gatekeeper of engineering productivity. Here, you will invent the techniques that allow the world's most advanced chips to reach the market."

Stack

Work on codebases that manage the largest designs on the planet.

Impact

Your optimizations reduce time-to-market for global tech giants.

Future-Proofing

Be part of the transition toward AI-accelerated chip design and cloud-scale verification.

Desirable Skills

• Knowledge of LLVM or similar compiler frameworks.
• Experience with Python for internal tooling and test automation.
• Familiarity with hardware verification environments (UVM).

The annual salary range for Massachusetts is $117,600 to $218,400. You may also be eligible to receive incentive compensation: bonus, equity, and benefits.