Principal EDA Software Engineer (C++, Characterization)

Cadence Design Systems; San Jose (CA); On-site; USD 136,500 - 253,500; Full time

Benefits offered by this job

401(k) plan with employer match

Employee stock purchase plan

Medical, dental, and vision plan options

Paid vacation and holidays

Job summary

A leading electronic design automation company in San Jose, California is seeking an experienced developer for EDA tools with expertise in C++. The ideal candidate will have over 8 years of relevant experience, strong knowledge of transistor-level timing analysis, and proficiency in software engineering principles. This role includes enhancing tool architecture, creating frameworks for advanced analysis, and applying machine learning technologies to improve performance significantly. A Bachelor’s degree in a relevant field is preferred, and the position offers a comprehensive benefits package along with a significant salary range.

Qualifications

• 8+ years of experience in the development of EDA tools.
• Experience in transistor-level timing, power, noise, aging, and reliability analysis.
• Strong proficiency in software engineering principles.

Responsibilities

• Enhance and expand existing tools' architecture for timing analysis.
• Create new frameworks for analyzing effects dominant at n5 and below.
• Leverage machine learning technology for performance improvements.

Skills

C++ knowledge

Data structures design

Algorithms

Transistor-level timing analysis

Education

BS in Computer Science, Electrical Engineering, or Computer Engineering

Job description

## **At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.**At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Join our expert R&D team as we create technologies and products that enable static and dynamic transistor-level analysis of the most advanced custom digital and mixed-signal circuits, powering the communication, IoT, and AI markets.## Key Responsibilities* Enhance and expand existing tools' architecture to cover timing analysis.* Create new frameworks for analyzing effects dominant at n5 and below.* Leverage machine learning technology to achieve significant improvements in speed, capacity, and usability over existing solutions.## Must-Have Qualifications* 8+ years of experience in development of EDA tools and expertise in one or more areas: transistor-level timing, power, noise, aging, reliability, and EMIR analysis.* Hardcore C++ knowledge, particularly in a Linux environment.* Strong proficiency in designing data structures, algorithms, and applying software engineering principles.* Industry experience developing and maintaining C++ based applications on Unix or Linux platforms.## Requirements* Experience with quality and software processes.* Proficiency in designing data structures, algorithms, and software engineering principles.* Ability to analyze transistor or gate-level schematics.* BS degree in Computer Science, Electrical Engineering, or Computer Engineering preferred.## Nice-to-Have Skills* Experience in development of circuit simulation or library characterization programs.* Understanding of SPICE simulation transistor models at a high level.* Experience with distributed programming, database design, and cloud APIs for distributed computing.At Cadence, you’ll work alongside industry leaders and innovators who are passionate about advancing technology. Your contributions will directly impact the development of cutting-edge tools and solutions for the communication, IoT, and AI industries. We foster a collaborative environment where your expertise and ideas will shape the technology of tomorrow.## Apply TodayIf you are ready to make a difference and push the boundaries of EDA technology, we encourage you to apply and join Cadence’s world-class R&D team.*The annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.*## **We’re doing work that matters. Help us solve what others can’t.****Equal Employment Opportunity Policy:**Cadence is committed to equal employment opportunity throughout all levels of the organization.We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact [e-mail].**Privacy Policy:**Job Applicant If you are a job seeker creating a profile using our careers website, please see the .E-Verify Cadence participates in theE-Verify program in certain U.S. locations as required by law.Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.