Senior Compiler Engineer - AI-Driven EDA & SV

Cadence; New Jersey; On-site; USD 118,000 - 218,000; Full time

Job summary

Cadence Design Systems is a leader in providing EDA software, hardware, and IP for complex IC design and electronic systems. The Senior Engineer in the System Verification Group will push the capabilities of the Xcelium compiler, tackle multi-billion gate challenges, and drive scalable verification for AI and neural processing units.

Join a team focused on language evolution, high-performance architectures, and rapid innovation in a world of AI-driven silicon design.

Qualifications

• BS with 10+ years, or MS with 7+, or PhD with 5+ years.
• 5+ years in Compiler Development, EDA, or HPC.
• Expert-level C++ (modern standards) and SystemVerilog/Verilog.
• Strong background in compiler theory: lexing, parsing, semantic analysis, code generation.
• Experience with multi-threading, memory management, and cache locality optimizations.

Responsibilities

• Design and implement SystemVerilog language extensions.
• Develop high-performance front-end and code generation components for the compiler.
• Conduct deep-dive bottleneck analyses and optimize C++ code for speed and memory footprint.
• Architect compiler and simulator tuned for complex AI designs and NPUs.
• Explore blue-sky features, including parallel and distributed compilation.

Skills

C++ (modern)

SystemVerilog

Compiler theory

Multi-threading

Memory management

Cache locality

LLVM familiarity

Python

UVM familiarity

Education

BS degree

MS degree

PhD

Tools

LLVM

Job description

Cadence Design Systems is a leader in providing EDA software, hardware, and IP for complex IC design and electronic systems. The Senior Engineer in the System Verification Group will push the capabilities of the Xcelium compiler, tackle multi-billion gate challenges, and drive scalable verification for AI and neural processing units.

Join a team focused on language evolution, high-performance architectures, and rapid innovation in a world of AI-driven silicon design.