Principal Product Tech Leader - AEC/SCM for AI Infra

Astera Labs

San Jose (CA)

Hybrid

USD 160,000 - 200,000

Full time

14 days+

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Job summary

Astera Labs in San Jose, CA seeks a hands-on Principal Product Technical Leader to drive product integration for Active Electrical Cables and Smart Cable Modules used in rack-scale AI infrastructure. You will own interfaces across silicon, firmware, PCB, cables, and mechanical design.

The role leads technical investigations, defines readiness criteria, and collaborates with customers and engineering teams to translate feedback into production-ready products.

Responsibilities

  • Define product-level interfaces, integration plans, risks, validation checkpoints, and readiness criteria from design through production release.
  • Influence architecture and design decisions across signal integrity, retimer and firmware integration, power, thermal, mechanical, manufacturability, cost, and schedule.
  • Lead product-level electrical compliance and system validation for AEC/SCM products, including channel performance, eye margins, jitter, equalization, link training, BER, interoperability, and resolution of system-level issues.
  • Direct and review AEC/SCM hardware validation, including board-level probing, circuit verification, functional testing under nominal, corner, mechanical, and environmental conditions, and reliability/failure analysis; ensure results are correlated to design requirements and corrective actions are driven to closure.
  • Drive root-cause analysis for issues spanning silicon, firmware, hardware, SI, mechanical, thermal, test, and manufacturing teams.

Job description

Principal Product Technical Leader — AEC/SCM

San Jose, California, United States

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .

Role Overview

Astera Labs is seeking a hands-on Principal Product Technical Leader to drive product integration for Active Electrical Cables (AECs) and Smart Cable Modules (SCMs) used in rack-scale AI infrastructure. You will serve as a technical owner across high-speed silicon and retimers, firmware, PCB or flex circuitry, cable assemblies, connectors, mechanical and thermal design, signal integrity, validation, manufacturing, and customers.

You will translate system and customer requirements, engineering data, and field feedback into reliable, production-ready products. This is an individual-contributor role: you will lead complex technical investigations, resolve cross-domain issues, strengthen product readiness, and improve repeatable integration and debug practices. You should bring deep expertise in at least one relevant discipline and working knowledge across adjacent domains.

Key Responsibilities
Product integration and validation
  • Define product-level interfaces, integration plans, risks, validation checkpoints, and readiness criteria from design through production release.
  • Influence architecture and design decisions early, finding creative, practical solutions to tradeoffs across signal integrity, retimer and firmware integration, power, thermal performance, mechanical constraints, manufacturability, cost, and schedule.
  • Lead product-level electrical compliance and system validation for AEC/SCM products, including channel performance, eye margins, jitter, equalization, link training, BER, interoperability, and resolution of system-level issues.
  • Direct and review AEC/SCM hardware validation, including board-level probing, circuit verification, functional testing under nominal, corner, mechanical, and environmental conditions, and reliability/failure analysis; ensure results are correlated to design requirements and corrective actions are driven to closure.
  • Drive root-cause analysis for issues spanning silicon, firmware, hardware, SI, mechanical, thermal, test, and manufacturing teams.
Production readiness and technical execution
  • Partner with NPI, manufacturing, quality, and operations teams to transition products from development into volume production.
  • Drive DFM/DFA/DFT reviews, production-test development, test-coverage improvements, yield analysis, and manufacturability feedback.
  • Own technical investigations and corrective actions for complex failures, process excursions, production escapes, and field issues.
  • Establish clear product specifications, issue-tracking practices, technical reports, and readiness reviews.
Customer and cross-functional leadership
  • Provide technical direction during customer bring-up, interoperability testing, platform qualification, and escalations.
  • Collaborate with applications and customer engineering teams to resolve design-in challenges and translate field feedback into product improvements.
  • Lead cross-functional design and integration reviews across hardware, firmware, SI, mechanical, test, manufacturing, and quality.
  • Mentor engineers and improve documentation, debug workflows, integration methods, and engineering standards.

The base salary range is $160,000 USD - $200,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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