Hardware Design Engineering, Senior Director - Signal Connectivity Rack-Scale Platforms

Astera Labs; San Jose (CA); On-site; USD 180,000 - 220,000; Full time

Job summary

Astera Labs in San Jose, California, is seeking a Senior Director for Hardware Design Engineering. This strategic role involves leading the engineering team responsible for product development of high-speed connectivity solutions. You will guide projects across electrical and mechanical design, validation, and OEM support.

Your leadership will be pivotal in developing innovative hardware solutions that align with customer needs and market trends. Candidates should have extensive experience in hardware design and management, with a strong focus on high-speed interconnects.

Qualifications

• Minimum 18 years of experience in hardware design engineering.
• At least 8 years in engineering management roles.
• Proven leadership in full product development lifecycle.

Responsibilities

• Lead and scale hardware design engineering organization.
• Manage development and validation of hardware products.
• Foster a culture of engineering excellence and cross-functional collaboration.

Skills

High-speed PCB design

Mechanical engineering

Hardware validation

Leadership and organization building

Interconnect technologies

Education

Bachelor's degree in Electrical Engineering or related

Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

About Astera Labs

Astera Labs is the connectivity backbone of rack-scale AI infrastructure. Our Active Electrical Cables (AEC), Smart Cable Modules (SCM), Silicon Evaluation Platforms, and rack-scale products deliver purpose-built, high-speed connectivity for the world's most demanding AI clusters. As our product portfolio expands in complexity, performance, and volume — and as OEM customers increasingly adopt Astera Labs silicon into their own designs — we need a senior engineering leader to build and scale the hardware design engineering organization that creates industry-defining products and enables our customers' success.

About The Role

We are hiring a Senior Director, Hardware Design Engineering to lead and scale Astera Labs' hardware design engineering organization across Active Electrical Cables (AEC), Smart Cable Modules (SCM), Silicon Evaluation Platforms (SVB/EVB), rack-scale products, and OEM/customer design enablement. This is a senior leadership role with full ownership of the hardware design function — encompassing electrical/PCB design, mechanical engineering, hardware validation, lab infrastructure, and customer hardware engineering support.

You will build and lead a world-class, multidisciplinary engineering organization that takes products from concept through design, validation, qualification, and production release — while simultaneously enabling OEM customers and design partners to successfully integrate Astera Labs silicon into their own products. Your teams will own the complete hardware realization of Astera Labs' connectivity products and serve as the technical bridge between Astera Labs' silicon capabilities and the broader ecosystem of customers building next-generation AI infrastructure.

You will be a key member of the engineering leadership team, driving technology roadmaps, making critical technical and business trade-off decisions, and partnering closely with silicon, firmware, signal integrity, NPI, manufacturing, quality, product management, sales, and customer-facing teams. You'll also be responsible for attracting, developing, and retaining top engineering talent as Astera Labs scales through hyper-growth.

Key Responsibilities

• Engineering Leadership & Organization Building
  • Lead and scale Astera Labs' hardware design engineering organization, encompassing:
  • Electrical/PCB Hardware Design Engineering — schematic capture, high-speed PCB/flex/substrate layout, power delivery, component engineering for cable modules through rack-scale systems
  • Mechanical Engineering — connector design, housing/enclosure design, thermal management, cable strain relief, chassis/sheet metal, form factor compliance, tolerance analysis
  • Hardware Validation Engineering — product-level electrical, mechanical, environmental, and reliability qualification and validation across all product lines
  • Lab Engineering & Infrastructure — test lab buildout, capital equipment strategy, measurement capability, and lab operations
  • Customer Hardware Engineering & OEM Enablement — reference design support, design reviews, integration guidance, and hands-on technical engagement with OEM customers adopting Astera Labs silicon
• Build, mentor, and lead a team of engineering managers and senior individual contributors across all hardware design disciplines
• Define organizational structure, hiring plans, career development frameworks, and technical competency models as the team scales
• Foster a culture of engineering excellence, rigorous design practices, cross-functional collaboration, and customer-centric technical support
• Represent the hardware design engineering function in executive reviews, board updates, and strategic planning sessions
• Define and manage the hardware technology roadmap for AEC, SCM, Silicon Evaluation Platforms, and rack-scale products — aligned with silicon roadmaps, customer requirements, market trends, and competitive dynamics
• Drive technology strategy decisions across interconnect architectures, PCB/substrate technologies, connector platforms, cable constructions, thermal solutions, chassis architectures, and form factors
• Identify and invest in next-generation hardware technologies (e.g., 224G/lane substrates, advanced thermal materials, novel connector interfaces, miniaturized form factors, liquid cooling integration) that maintain Astera Labs' competitive differentiation
• Partner with Product Management and Business Development to translate customer needs, market requirements, and standards evolution into engineering development priorities
• Align hardware design roadmap with silicon tape-out schedules, firmware development timelines, manufacturing readiness milestones, and OEM customer design-in timelines
• Incorporate customer and OEM feedback into technology roadmap decisions — ensuring reference designs, evaluation platforms, and design collateral evolve to meet ecosystem needs
• Drive R&D and new product development for the full range of hardware products — from cable-scale modules to rack-scale systems
• Oversee products through the full design lifecycle — from architecture definition, schematic/layout design, mechanical design, prototype build, validation, qualification, to production release
• Ensure rigorous design review processes at each stage (architecture, schematic, layout, mechanical, pre-production) with clear entry/exit criteria and cross-functional participation
• Make critical technical trade-off decisions that balance performance, cost, manufacturability, schedule, and risk across the product portfolio
• Drive schedule discipline and engineering milestone execution — ensuring products hit market windows aligned with customer platform cycles and silicon availability
• Oversee high-speed PCB, flex circuit, and substrate design across the full product portfolio
• Ensure designs meet signal integrity requirements for 112G and 224G PAM4 lanes, including impedance control, loss budgets, crosstalk isolation, and return loss compliance
• Drive component engineering decisions — selecting connectors, passives, power management ICs, and materials that meet performance, reliability, cost, and availability requirements
• Establish and enforce design rules, layout guidelines, stackup definitions, and PCB/substrate technology selection criteria across all product lines
• Partner with Signal Integrity engineering to validate designs through simulation and correlation with measured performance
• Direct mechanical engineering across the full product range, ensuring products meet relevant form factor standards and drive thermal management design across all product lines
• Own the hardware validation strategy and execution for all products
• Define validation plans that provide comprehensive coverage across signal integrity performance, power delivery, thermal behavior, mechanical durability, and environmental resilience
• Establish qualification programs aligned with customer requirements, industry standards, and internal reliability targets
• Drive a data-driven validation culture and oversee interoperability testing with customer host platforms, switches, NICs, and system environments
• Define and execute the strategy for Astera Labs' hardware engineering labs
• Drive capital equipment planning, procurement, and installation for lab infrastructure that supports high-bandwidth measurement and system-level testing
• Ensure lab environments support rapid prototyping, debug, validation, and failure analysis workflows across all product lines
• Build and lead a lab engineering team responsible for equipment maintenance, calibration, measurement methodology, and lab operations
• Lead hardware engineering engagement with OEM customers who are designing Astera Labs silicon into their own products
• Provide design review support for customer hardware designs incorporating Astera Labs retimers, re-drivers, and connectivity ASICs
• Develop and maintain comprehensive reference design packages, design guides, integration manuals, and best-practice documentation for OEM customers
• Build and lead a customer hardware engineering support function that provides responsive, expert-level technical assistance to OEM customers during their design and integration cycles
• Support customer bring-up, debug, and troubleshooting activities and drive resolution of customer-reported hardware issues
• Establish escalation processes and service-level expectations for customer hardware engineering support
• Collaborate with silicon design teams to provide hardware-level feedback on package design, pin assignment, power requirements, and thermal specifications
• Partner with Sales, FAE, and Product Management teams to identify high-value customer engagements and prioritize hardware engineering support resources
• Engage with Quality and Reliability teams to ensure products meet Astera Labs' quality standards and customer reliability expectations
• Interface with Product Management to align development priorities with market opportunities, customer requirements, and business objectives
• Collaborate with Firmware Engineering to ensure hardware-firmware co-design and with Manufacturing Engineering to ensure designs are manufacturable and testable at volume
• Represent Astera Labs in industry standards bodies, MSAs, and technical working groups
• Ensure hardware designs comply with relevant industry standards — IEEE 802.3ck/dj, OIF CEI-112G/224G, SFF-TA (OSFP, QSFP-DD), CMIS, OCP specifications, and emerging rack-scale standards
• Monitor competitive landscape, emerging technologies, and standards evolution to inform roadmap and design decisions

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical discipline
• 18+ years of progressive experience in hardware design engineering for high-speed interconnect, transceiver/module, cable assembly, evaluation platforms, or rack-scale system products
• 8+ years in engineering management/leadership roles, including managing managers and building multi-team organizations
• Proven track record leading engineering teams through full product development lifecycle — from concept through qualification and volume production
• Deep technical expertise in high-speed PCB/substrate design, signal integrity, power delivery, and mixed-signal circuit design at 56G/112G PAM4 data rates or above
• Strong background in mechanical engineering for interconnect and system products — connector design, thermal management, chassis architecture, and form factor compliance
• Demonstrated experience establishing and executing hardware validation and qualification programs for high-reliability products
• Experience building and managing hardware engineering lab infrastructure and measurement capabilities
• Proven experience engaging with OEM customers on hardware design enablement — design reviews, reference design development, and customer technical support for silicon/ASIC integration
• Proven ability to make both strategic technology decisions and detailed technical trade-offs that balance performance, cost, schedule, and manufacturability
• Experience managing engineering teams through hyper-growth — scaling organizations, processes, and infrastructure simultaneously
• Strong executive communication skills — able to present technology strategy, program status, and risk assessments to C-level leadership and customer executives
• Experience partnering with contract manufacturers and ODMs in Asia for hardware product realization

Preferred Qualifications

• Master's or Ph.D. in Electrical Engineering with emphasis on high-speed interconnects, electromagnetic design, or mixed-signal systems
• Direct experience developing Active Electrical Cables (AEC), Smart Cable Modules (SCM), optical transceivers, or high-speed cable/connector assemblies
• Experience designing silicon evaluation platforms (EVBs/SVBs) for complex SoCs, ASICs, or connectivity silicon
• Experience developing rack-scale or chassis-class hardware products for data center, hyperscale, or AI infrastructure applications (switch chassis, OCP systems, or equivalent)
• Track record of successful OEM design enablement — helping customers achieve first-pass success integrating complex semiconductor products into their hardware platforms
• Experience building and scaling customer-facing hardware engineering support organizations
• Experience with 224G/lane (1.6T aggregate) interconnect technology and next-generation substrate/connector/cable architectures
• Track record delivering connectivity products to hyperscale customers (AWS, Google, Microsoft, Meta, NVIDIA, or equivalent) for AI/ML infrastructure applications
• Experience integrating retimer ASICs into cable module or system-level products
• Deep familiarity with relevant standards: IEEE 802.3ck/dj, OIF CEI-112G/224G, SFF-8636, CMIS 5.x+, OSFP, QSFP-DD, OCP specifications
• Experience with rack-scale system design including power distribution, thermal/airflow architecture, BMC/management interfaces, and high-density backplane/midplane design
• Background in FMEA, DFMEA, robust design methodologies, and six-sigma quality approaches
• Mandarin language proficiency for direct engagement with manufacturing partners in China
• Experience with simulation and EDA tools (Cadence Allegro/OrCAD, Ansys HFSS/SIwave, Keysight ADS, SolidWorks/Creo, thermal/CFD simulation tools)

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.