Principal Product Engineer - IC NPI & Yield Leader

Celero Communications, Inc.; San Jose (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Celero Communications is seeking a hands‑on Principal Product Engineer to lead the transition of its coherent DSP ICs from development to qualified, high‑yield manufacturing. You will define and execute productization strategies across NPI, reliability, test, quality, and ramp for Known Good Die and packaged products.

You will drive end‑to‑end NPI, define milestones, and work closely with silicons, design, test, supply chain, and operations to ensure manufacturable launches.

Qualifications

• Bachelor’s degree in electrical engineering or related fields.
• Master’s degree preferred.
• 10+ years of experience in product engineering, silicon manufacturing, reliability engineering, or related IC lifecycle roles.
• Proven experience taking complex ICs from first silicon through qualification and volume manufacturing.
• Experience with wafer‑level test, Known Good Die (KGD), and production test flows.
• Strong analytical skills and comfort working directly with large manufacturing and test data sets.

Responsibilities

• Drive end‑to‑end NPI execution from first silicon through qualification, sampling, and volume production.
• Define NPI milestones, readiness criteria, and exit conditions across design, test, reliability, manufacturing, and operations.
• Work with silicon design, DFT, test engineering, supply chain, and operations to ensure manufacturable product launches.
• Identify technical and operational risks early and lead mitigation through data‑driven decisions.
• Define and execute reliability and qualification strategies for advanced‑node coherent DSP ICs, including KGD qualification.
• Develop and own reliability stress plans (HTOL, HTSL, temperature cycling, ESD, latch‑up, early‑life failure).
• Manage external reliability lab execution, including coverage definition, scheduling, reporting, and failure analysis.
• Analyze qualification data and drive product release readiness based on measured risk and maturity.
• Define internal product quality targets aligned with application and market requirements.
• Own quality metrics related to silicon maturity, yield stability, and manufacturing readiness.
• Drive root‑cause analysis for quality or reliability excursions and lead corrective actions.
• Support customer quality discussions as needed, primarily through preparation of data and technical analysis.
• Lead technical engagement with foundry and OSAT partners from wafer fabrication through back‑end processing and shipment.
• Define and refine production test strategies with test engineering, balancing coverage, cost, yield, and guard‑banding.
• Drive engineering builds, characterization lots, and production ramps.
• Ensuring robust handoff from engineering tests flows to stable production manufacturing.
• Own yield learning and yield optimization from early silicon through high‑volume manufacturing.
• Perform deep analysis of wafer sort, die sort, and final test data to identify yield limiters.
• Drive cross‑functional corrective actions across design, process, test, and manufacturing.
• Establish yield targets, dashboards, and regular yield reviews to support sustained volume production.

Skills

Analytical skills

Cross‑functional collaboration

Data‑driven decision making

Technical execution bias

Education

Bachelor's degree in Electrical Engineering

Master's degree preferred

Tools

Wafer‑level test

KGD (Known Good Die)

Job description

Celero Communications is seeking a hands‑on Principal Product Engineer to lead the transition of its coherent DSP ICs from development to qualified, high‑yield manufacturing. You will define and execute productization strategies across NPI, reliability, test, quality, and ramp for Known Good Die and packaged products.

You will drive end‑to‑end NPI, define milestones, and work closely with silicons, design, test, supply chain, and operations to ensure manufacturable launches.