Principal NoC IP Architect for High-Perf FPGA Interconnect

Altera; San Jose (CA); On-site; USD 210,000 - 299,000; Full time

Job summary

Altera is seeking a Principal NoC IP Micro-Architect in San Jose, CA to lead end-to-end NoC IP architecture, RTL design, and integration into next‑gen FPGA platforms. You will collaborate across architecture, design, verification, software, physical design, and product teams to deliver high‑performance, power‑efficient interconnects.

This highly visible role requires deep expertise in SoC interconnects, NoC fabrics, RTL development, performance modeling, and system‑level optimization.

Qualifications

• Bachelor's or Master's Degree in Electrical Engineering, Computer Engineering, or a related field with 15+ years of related working experience.
• 10+ years of experience in SystemVerilog, VCS/Synopsys simulators, Lint and Synthesis.
• 10+ years of experience in programming with C/C++/Perl/Python/TCL/Unix Shell script.
• 10+ years of experience in FPGA design and programming is a plus.
• 10+ years of experience in RTL validation is a plus.
• 10+ years of experience in development of Network on Chip IPs.
• 5+ years of experience with the usage of AI in development processes for higher efficiency would be a plus.

Responsibilities

• Develops RTL, registers, and high-level design for NoC IPs and related FPGA IPs for full-chip integration.
• Contributes to architecture and microarchitecture feature definitions.
• Creates prototypes, simulations, and system requirements.
• Prepares logic diagrams and codes for system design and test specs.
• Generates device-level bring-up software models and timing/power data.
• Applies RTL implementation to meet power, performance, and area goals with PD collaboration.
• Leads design quality via timing, lint, CDC, RDC, DFT and automation.
• Mentors senior engineers and guides the NOC team through blockers and project challenges.

Skills

SystemVerilog

RTL design

VCS/Synopsys simulators

Lint & Synthesis

C/C++/Perl/Python/TCL/Unix Shell

FPGA design

RTL validation

Network on Chip IPs

AI in development process

Education

Bachelor's or Master's Degree in Electrical/Computer Engineering or related field

Tools

VCS

Synopsys tools

Job description

Altera is seeking a Principal NoC IP Micro-Architect in San Jose, CA to lead end-to-end NoC IP architecture, RTL design, and integration into next‑gen FPGA platforms. You will collaborate across architecture, design, verification, software, physical design, and product teams to deliver high‑performance, power‑efficient interconnects.

This highly visible role requires deep expertise in SoC interconnects, NoC fabrics, RTL development, performance modeling, and system‑level optimization.