FPGA IP Software Engineer – HW/SW Co-Design & Acceleration

Altera Corporation

San Jose (CA)

On-site

USD 133,000 - 213,000

Full time

3 days ago
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Job summary

Altera is seeking an FPGA IP Software Development Engineer in San Jose to design, integrate, and debug FPGA-based systems for embedded networking and acceleration projects, including PCIe, HPS, EMIF, and Ethernet IPs.

You will collaborate with hardware and software teams on HW/SW co-design, board bring-up, and development of software abstractions and drivers to enable FPGA acceleration in SmartNICs and ARM-based FPGA systems.

Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Engineering, CS; Masters preferred.
  • 3+ years of FPGA design and development experience.
  • Strong RTL development with Verilog and SystemVerilog.
  • Experience integrating PCIe, Ethernet, EMIF, and ARM HPS IPs.
  • Experience with FPGA system bring-up, validation, debugging.
  • Familiarity with FPGA toolchains and implementation flows.

Responsibilities

  • Design, develop, integrate, and validate RTL for FPGA-based systems and platforms.
  • Collaborate with software and hardware teams on FPGA HW/SW co-design and integration.
  • Develop software abstractions, drivers, and frameworks for FPGA acceleration solutions.
  • Support board bring-up, system-level validation, and debugging.
  • Participate in architecture discussions and technical reviews.

Skills

FPGA design
Verilog
SystemVerilog
RTL development
PCIe
Ethernet IPs
ARM HPS
C/C++
Python
Embedded Linux

Education

Bachelor's degree in Electrical Engineering
Master's degree preferred

Tools

Vivado
Quartus

Job description

Altera is seeking an FPGA IP Software Development Engineer in San Jose to design, integrate, and debug FPGA-based systems for embedded networking and acceleration projects, including PCIe, HPS, EMIF, and Ethernet IPs.

You will collaborate with hardware and software teams on HW/SW co-design, board bring-up, and development of software abstractions and drivers to enable FPGA acceleration in SmartNICs and ARM-based FPGA systems.

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