Principal, MTS, DRAM Systems Architect

Micron Technology, Inc; Boise (ID); On-site; USD 190,000 - 230,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time off

Paid holidays

Job summary

Micron Technology, Inc. seeks a Principal/Member of Technical Staff (MTS) IO/Clock Design Eng to join the DRAM IP Design team for high-speed IP circuits used in Micron's DRAM products.

Relocation to Boise, Idaho is required; you will develop, verify, and optimize IO and clocking circuits, analyze timing, jitter and duty cycle impacts, and drive AI-assisted design methods. Responsibilities include modeling, simulation, and collaboration with process and data science teams to push performance in

Qualifications

• Design high-speed IO interface and clocking circuits with proven silicon experience.
• Lead layout supervision to minimize parasitics in high-speed circuits.
• Excellent communication to share technical concepts with peers.

Responsibilities

• Innovate, design, optimize and verify high-speed IO and clocking circuits in DRAM products.
• Assess timing and jitter sensitivity at circuit and full-chip levels.
• Develop modeling and simulation methods for key circuit metrics and their impact on specs.
• Collaborate with Product Engineering and SI teams to compare silicon with simulations.
• Work with process integration and transistor modeling teams on new process nodes.
• Collaborate with data science teams and AI vendors to improve AI-assisted design flow.

Skills

High-speed IO

Clocking circuits

Timing analysis

Mentoring engineers

Python/Perl scripting

AI-assisted design

Education

MSEE with 10+ years

BSEE with 12+ years

Tools

PERL

Python

Job description

Req ID: JR103094 Principal, MTS, DRAM Systems Architect

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

We are seeking a Principal/Member of Technical Staff (MTS) IO/Clock Design Eng to join our DRAM IP Design team and contribute to the development of critical high-speed IP circuits used across Micron’s DRAM memory products. In this role, you will be responsible for the design, development, optimization, verification, and technical support of these high-speed IPs. You will focus on equalization and bandwidth extension to push the limits of circuit and process performance, analyze IO impairments as well as clock jitter and duty cycle distortion, and assess their impact on DRAM system timing. You will also develop and implement effective engineering solutions to address these challenges.

Relocation to Micron headquarter in Boise, Idaho is required for this position.

Responsibilities

• Innovate, design, optimize and verify high-speed IO and clocking circuits used in new DRAM products.
• Apply robust high-speed circuit design techniques and enhance critical performance evaluation, including timing and jitter sensitivity, of the IO data path and clock path at circuit and full-chip level.
• Develop accurate modeling, analysis and simulation methodology to capture key circuit performance metrics and their impact to product specifications at full-chip and system level.
• Work with Product Engineering and SI team to compare silicon performance with simulation results and support correlation activities.
• Collaborate with process integration and transistor modeling teams on Micron's next groundbreaking process node.
• Work with the internal data science team and EDA vendors to leverage and improve AI-assisted design flow and circuits optimization.

Minimum Qualifications

• Minimum MSEE + 10 years or BSEE + 12 years of industry experience with strong background in designing high-speed IO interface, timing and clocking circuits with proven silicon successes.
• Ability to supervise layout work and understand good layout practices for high-speed circuits to minimize parasitic impacts.
• Strong interpersonal skills with the ability to convey sophisticated technical concepts to other design peers both verbally and written.
• Mental agility and ability to multi-task is a must for this position as we work with all product types (commodity, mobile, graphics) and product teams in parallel with silicon validation efforts.

Preferred Qualifications

• Prior experience in DRAM circuit design experience.
• Prior experience in channel modeling and characterization, transceiver noise and timing budget analysis, equalization techniques, SI knowledge, etc.
• Understanding of device physics and basic CMOS processing techniques.
• Demonstrated ability in mentoring and coaching engineers early in their careers.
• Demonstrated ability with AI/ML usage and fluency in scripting languages such as PERL/Python.
• Use of Agentic AI

Job Profile(s): Semiconductor Design Eng MTS

Relocation Level: TBD

Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on Benefits | Micron Technology, Inc

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.