DRAM Memory Design Engineer - Principal | MTS | SMTS

Micron Technology, Inc; Boise (ID); On-site; USD 180,000 - 260,000; Full time

Benefits offered by this job

Relocation assistance

Medical, dental, vision plans

Paid time off

Holiday pay

Job summary

Micron Technology, Inc in Boise, ID seeks a Principal SMTS/ MTS DRAM Memory Design Engineer to lead digital and analog circuit design for next-generation memory products. You will drive verification, silicon validation, and parasitic analysis while guiding optimization efforts.

The role requires strong leadership, cross-functional collaboration, and expertise in Verilog, PDN analysis, and AI-assisted design flows. On-site 5 days with relocation support possible.

Qualifications

• Bachelor's in Electrical Engineering with 10+ years for BSEE track or 15+ years for SMTS track.
• Strong CMOS circuit design knowledge and Verilog modeling experience.
• Experience with design verification methodologies and power delivery networks.

Responsibilities

• Design and optimize digital and analog circuits for next-generation DRAM products.
• Lead circuit development, simulation, verification, and silicon validation.
• Drive floor-planning, layout optimization, and tape-out activities.
• Mentor engineers and collaborate across internal/external partners.

Skills

CMOS circuit design

Verilog

Design verification

Scripting (Python/Tcl/Perl)

Analytical thinking

Cross-functional collaboration

Education

Bachelor's degree in Electrical Engineering

MSEE or related master's preferred

15+ years semiconductor design experience (SMTS path)

Tools

HSPICE

FINESIM

PDN analysis tools

Job description

DRAM Memory Design Engineer - Principal | MTS | SMTS

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

We are shaping the memory technologies that power today's most advanced computing platforms, from AI accelerators to mobile and client devices. Our DRAM Engineering team brings together skilled engineers across the globe to solve complex technical challenges, drive innovation, and deliver high-performance memory solutions. If you enjoy tackling difficult problems and turning ideas into products, you'll find exciting opportunities to make an impact here.

Responsibilities:

• Design and optimize digital and analog circuits for next-generation DRAM products, including memory arrays, control logic, datapaths, address decoding, and I/O circuitry.
• Lead circuit development, simulation, verification, and silicon validation to achieve performance, power, area, and quality targets.
• Drive floor-planning, layout optimization, parasitic analysis, and tape-out activities.
• Advance AI-assisted design, automation, and design-space exploration through collaboration with internal and external partners.
• Provide technical leadership through innovation, multi-functional collaboration, and mentorship of other engineers.

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering or related field, plus MSEE with 10+ years, BSEE with 12+ years, or equivalent relevant semiconductor design experience; SMTS candidates typically have 15+ years of experience with demonstrated technical leadership.
• Extensive knowledge of CMOS circuit design, device physics, state machine logic, and design verification methodologies.
• Experience with Verilog modeling, simulation tools, and power delivery network (PDN) analysis.
• Proficiency in scripting languages such as Python, Tcl, or Perl.
• Strong analytical, problem-solving, communication, and multi-functional collaboration skills.

Preferred Qualifications:

• Master's degree or PhD in Electrical Engineering or a related field.
• Experience with DDR5, LPDDR5/LPDDR6, GDDR6/7, or HBM3/HBM4 memory technologies.
• Experience with FINESIM, HSPICE, or similar schematic entry and simulation tools.
• Experience leading complex circuit design projects and mentoring engineers.
• Exposure to AI/ML-assisted design flows, agentic AI, or advanced design automation frameworks.

Work location: Boise, ID, Main Site. Schedule is 5 days onsite. Relocation support may be available.

Job Profile(s):

Semiconductor Design Engineer 5 - Semiconductor Design Eng SMTS

Relocation Level: TBD

Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future.

• We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget.
• Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave.
• Additionally, Micron benefits include a robust paid time-off program and paid holidays.

For additional information regarding the Benefit programs available, please see the Benefits Guide posted on Benefits | Micron Technology, Inc

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.