Principal IC Package Design Engineer

Ethernovia; San Jose (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Ethernovia, Inc. in San Jose is seeking a Principal IC Package Design Engineer to lead the architecture, design, and execution of advanced packaging for our Ethernet switches and PHYs.

You will own the full package lifecycle from feasibility to mass production, collaborating with Silicon, PCB, and OSAT teams to meet high-speed SerDes targets and reliable automotive-grade requirements. Join a fast-growing team shaping the future of mobility with breakthrough packaging technology and

Qualifications

• Minimum of a B.S. in Electrical Engineering or related field.
• 10+ years in IC package design and architecture.
• Experience with high-speed networking or automotive electronics is preferred.

Responsibilities

• Lead package architecture & feasibility assessments for high-performance Ethernet switches and PHYs.
• Execute complex, multi-layer packages (FCBGA, SiP, MCM) with advanced stack-ups.
• Perform SI/PI and thermal co-design with Signal/Power Integrity and Thermal engineers.
• Define substrate design rules and manage routing, DFM/DFA constraints.
• Engage with OSATs and vendors for NPI and production ramp.
• Bridge Silicon IC Design and System/PCB teams for co-design optimization.
• Track and influence technology roadmap for advanced packaging trends.

Skills

High-speed packaging

SerDes knowledge

Cross-functional leadership

Data-driven decision making

Automotive electronics

Education

B.S. in Electrical Engineering

Tools

Cadence Allegro APD

SiP Layout

Synopsys 3DIC Compiler

HFSS

Q3D

Cadence Clarity

Job description

About Ethernovia, Inc.

Ethernovia is developing the future of Ethernet-based networks to realize the full potential of software-defined and autonomous vehicles, robotics and other intelligent machines. Founded in 2018, the company's breakthrough data transport and acceleration technology is ushering in a new era of connectivity and capabilities in the vehicle and at the edge, including highly reliable autonomy, over-the-air servicing and AI-backed applications.

About Ethernovia, Inc.

Ethernovia is developing the future of Ethernet-based networks to realize the full potential of software-defined and autonomous vehicles, robotics and other intelligent machines. Founded in 2018, the company's breakthrough data transport and acceleration technology is ushering in a new era of connectivity and capabilities in the vehicle and at the edge, including highly reliable autonomy, over-the-air servicing and AI-backed applications.

Ethernovia's co-founders are serial technology entrepreneurs with multiple prior successful ventures together. We are well-funded and backed by some of the worlds' leading technology investors, having secured $154M ($90+M Series-B and $64M Series-A) in total funding to date:

• Ethernovia Raises Over $90 Million Series B to Scale Leading-Edge Autonomy and Physical AI Networking Chips
• Ethernovia Raises $64 Million to Accelerate the Revolution of Vehicle Networks | Business Wire
• • (financial backers include: Porsche SE, Qualcomm, AMD, Western Digital, Maverick Silicon, Socratic Partners, Conduit Capital, and CDIB-TEN Capital)

Ethernovia has been recognized in EE Times' prestigious list of the Top 100 Startups for 2025.

• March 2026: Ethernovia Announces HSB-Enabled Networking Board for NVIDIA Holoscan Platforms
• January 2024: Our CEO Ramin Shirani Named MotorTrend Software-Defined Vehicle Innovator Awards Winner (ethernovia.com)
• September 2023: Continental and Ethernovia Announce Partnership to Develop Automotive Switch in 7nm - Ethernovia
• Connected Car News: Helios, Continental, Ethernovia, Avanci, BMW, Mapbox, Porsche, SEMA, Honda, UltraSense, Flex Logix, Diodes Inc., Garmin, Toyota & Caruso | auto connected car news

With talented employees on 4 continents, we have filed 50+ patents to date.

Join Ethernovia's team to make a lasting impact on the future of packet processor-centric networking solutions to support the real-time sensor, Physical AI, and control data demands of software-defined autonomy across vehicles, robots and intelligent machines.

Come share in our success with pre-IPO shares, competitive compensation, and great benefits while growing your knowledge and career with world-class talent. We are looking for talented engineers and leaders who have an entrepreneurial spirit and want to drive cutting-edge designs from concept to silicon to the future of mobility.

Principal IC Package Design Engineer

Summary:

We are seeking a visionary and deeply technical Principal IC Package Design Engineer to lead the architecture, design, and execution of advanced packaging solutions for our next-generation Ethernet switches and PHYs. You will be responsible for the entire package lifecycle—from early-stage feasibility and architectural definition to detailed layout, signal/power integrity (SI/PI) co-design, thermal management, and mass production release.

Key Responsibilities

• Package Architecture & Feasibility: Lead the definition of package concepts, substrate stack-ups, bump/ball maps, and pinouts to optimize for system cost, electrical performance, and thermal constraints.
• Detailed Package Design: Execute complex, high-speed, multi-layer package layouts (FCBGA, FCCSP, SiP) utilizing industry-standard EDA tools.
• SI/PI & Thermal Co-Design: Partner closely with Signal/Power Integrity and Thermal engineers to ensure package designs meet stringent targets for high-speed SerDes (56G/112G+), power delivery networks (PDN), and thermal dissipation.
• Substrate Design Integration: Define design rules and manage substrate layout, routing optimization, and manufacturing constraints (DFM/DFA).
• OSAT & Vendor Management: Drive technical engagements with leading substrate suppliers and OSATs. Evaluate vendor capabilities, negotiate design rules, and resolve manufacturing/assembly issues during NPI (New Product Introduction) and production ramp.
• Cross-Functional Collaboration: Act as the bridge between Silicon IC Design and System/PCB teams to ensure seamless chip-package-board co-design and optimization.
• Technology Roadmap: Stay at the forefront of semiconductor packaging trends (e.g., advanced organic substrates, glass substrates, co-packaged optics) to influence Ethernovia's long-term hardware roadmap.

Qualifications & Skills

Required Experience:

• Education: B.S. in Electrical Engineering, Materials Science, Mechanical Engineering, or a related field.
• 10+ years of direct experience in IC package design and architecture, ideally within high-speed networking, automotive electronics, or high-performance computing (HPC).

Technical Expertise:

• Advanced Packaging: Proven track record of delivering high-volume, complex Flip-Chip BGA (FCBGA), System-in-Package (SiP), and multi-chip module (MCM) designs.
• EDA Tools: Expert proficiency in package design suites such as Cadence Allegro Package Designer (APD), SiP Layout, or Synopsys 3DIC Compiler.
• Signal & Power Integrity Foundations: Strong understanding of electromagnetic theory, transmission lines, crosstalk, and PDN concepts. Familiarity with extraction tools (Ansys HFSS/Q3D, Cadence Clarity) is highly desirable.
• Manufacturing Knowledge: Deep understanding of substrate fabrication processes, assembly line limits, and automotive-grade reliability standards (e.g., AEC-Q100 guidelines).

Leadership & Soft Skills:

• Strong problem-solving abilities with a data-driven approach to architectural trade