Lead Systems/DSP Engineer

Ethernovia; San Jose (CA); On-site; USD 180,000 - 250,000; Full time

Benefits offered by this job

Medical, dental, and vision insurance

Pre IPO stock options

Flexible hours

Job summary

Ethernovia in San Jose is seeking a Lead Systems/DSP Engineer to lead the design of next-generation high-speed physical layer (PHY). In this role, you will define the DSP architecture from system-level modeling to silicon validation.

You will play a crucial technical leadership role, collaborating with cross-functional teams to translate advanced algorithms into robust, production-ready silicon for high-performance transceiver implementations. This position offers competitive compensation, pre-IPO shares, and growth opportunities.

Qualifications

• 10+ years of experience in DSP/system architecture for high-speed communication systems.
• Deep expertise in digital communications theory and advanced equalization algorithms.
• Proven track record of driving complex systems from concept to silicon.

Responsibilities

• Define and own the DSP/system architecture for high-speed transceivers.
• Drive key architectural decisions across DSP, analog front-end, and system partitioning.
• Develop and maintain high-fidelity system models of complete transceivers.

Skills

DSP/system architecture

Digital communications theory

System modeling tools (MATLAB, Simulink, Python, C++)

Mixed-signal design fundamentals

Education

MS or PhD in Electrical Engineering or related discipline

Tools

MATLAB

Simulink

Python

C++

Job description

About Ethernovia, Inc.

Ethernovia is developing the future of Ethernet-based networks to realize the full potential of software‑defined and autonomous vehicles, robotics and other intelligent machines. Founded in 2018, the company’s breakthrough data transport and acceleration technology is ushering in a new era of connectivity and capabilities in the vehicle and at the edge, including highly reliable autonomy, over‑the‑air servicing and AI‑backed applications.

Ethernovia's co‑founders are serial technology entrepreneurs with multiple prior successful ventures together. We are well‑funded and backed by some of the worlds’ leading technology investors, having secured $154M ($90+M Series‑B and $64M Series‑A) in total funding to date:

• Ethernovia Raises Over $90 Million Series B to Scale Leading‑Edge Autonomy and Physical AI Networking Chips
• Ethernovia Raises $64 Million to Accelerate the Revolution of Vehicle Networks | Business Wire
  • (financial backers include: Porsche SE, Qualcomm, AMD, Western Digital, Maverick Silicon, Socratic Partners, Conduit Capital, and CDIB‑TEN Capital)

Ethernovia has been recognized in EE Times' prestigious list of the Top 100 Startups for 2025.

• March 2026: Ethernovia Announces HSB‑Enabled Networking Board for NVIDIA Holoscan Platforms
• January 2024: Our CEO Ramin Shirani Named MotorTrend Software‑Defined Vehicle Innovator Awards Winner (ethernovia.com)
• September 2023: Continental and Ethernovia Announce Partnership to Develop Automotive Switch in 7nm - Ethernovia
• Connected Car News: Helios, Continental, Ethernovia, Avanci, BMW, Mapbox, Porsche, SEMA, Honda, UltraSense, Flex Logix, Diodes Inc., Garmin, Toyota & Caruso | auto connected car news

With talented employees on 4 continents, we have filed 50+ patents to date.

Join Ethernovia’s team to make a lasting impact on the future of packet processor‑centric networking solutions to support the real‑time sensor, Physical AI, and control data demands of software‑defined autonomy across vehicles, robots and intelligent machines. Come share in our success with pre‑IPO shares, competitive compensation, and great benefits while growing your knowledge and career with world‑class talent. We are looking for talented engineers and leaders who have an entrepreneurial spirit and want to drive cutting edge designs from concept to silicon to the future of mobility.

Lead Systems/DSP Engineer

Summary

We are seeking a seasoned DSP / System Architect to lead the design of next‑generation high‑speed (25G+) physical layer (PHY). In this role, you will define and drive the end‑to‑end DSP architecture, from system‑level modeling through silicon validation, enabling highly optimized, low‑power, and high‑performance transceiver implementations.

This is a high‑impact technical leadership role at the intersection of signal processing, mixed‑signal design, and system architecture. You will work closely with cross‑functional teams to translate advanced algorithms into robust, production‑ready silicon.

Key Responsibilities

System Architecture & Technical Leadership

• Define and own the DSP/system architecture for high‑speed transceivers, balancing power, performance, and silicon area
• Drive key architectural decisions across DSP, analog front‑end, and system partitioning
• Lead system‑level trade‑offs and provide technical direction across the organization

Modeling & Algorithm Development

• Develop and maintain high‑fidelity system models of complete transceivers using MATLAB, Simulink, Python, and/or C++
• Design, evaluate, and optimize advanced equalization techniques, including FFE, DFE and MLSD
• Architect robust Clock and Data Recovery (CDR) solutions with wide frequency acquisition range and very low phase noise
• Develop efficient and advanced echo cancellation algorithms for full‑duplex high‑speed links optimizing for power and silicon area
• Design adaptive DSP algorithms with strong focus on rate of convergence, robustness, and implementation efficiency
• Develop channel model including nonlinear effects and complex noise sources

System Integration & Cross‑Functional Collaboration

• Translate system‑level requirements into block‑level specifications (AFE, ADC/DAC, PLL, DSP blocks, etc.)
• Collaborate closely with analog, RTL, and physical design teams to ensure accurate and efficient implementation
• Ensure alignment between algorithm models and hardware realization

Silicon Validation & Productization

• Drive pre‑silicon to post‑silicon correlation, ensuring models accurately predict silicon behavior
• Define and support silicon bring‑up, characterization, and debugging
• Establish lab validation methodologies and support compliance testing and performance benchmarking
• Contribute to system‑level bring‑up and production ramp readiness

Qualifications

Required

• MS or PhD in Electrical Engineering or a related discipline
• 10+ years of experience in DSP/system architecture for high‑speed communication systems
• Deep expertise in digital communications theory including advanced, efficient and adaptive equalization and echo cancellation algorithms, CDR algorithms, phase noise characterization and loop dynamic analysis, channel modeling and nonlinear effects
• Strong hands‑on experience with system modeling tools (MATLAB, Simulink, Python, C++)
• Solid understanding of mixed‑signal design fundamentals, including ADC/DAC architectures, PLL behavior and phase noise analysis, channel and analog front‑end modeling including non‑idealities
• Proven track record of driving complex systems from concept to silicon

Preferred

• Experience in designing high‑speed IEEE 802.3 transceivers for automotive, robotics and data center applications over both optical and copper channels
• Prior technical leadership or mentoring experience

What You Can Expect From Ethernovia

• Technology depth and breadth expansion that can’t be found in a large company
• Opportunity to grow your career as the company grows
• Pre IPO stock options
• Cutting edge technology
• World class team
• Competitive base salary
• Flexible hours
• Medical, dental and vision insurance for employees

Salary Range

• The actual offered base salary for U.S. locations will vary depending on factors such as work location, individual qualifications, specializations, years of experience, skills, job‑related knowledge, and internal equity. The annual salary range for this position is $180,000 - $250,000. The compensation package will also include incentive compensation in the form of pre‑IPO ISO options, in addition to base salary and a full range of medical and other benefits.

* Principals Only (No Agencies)