Principal IC Package Design Engineer

Ethernovia, Inc.; San Jose (CA); On-site; USD 200,000 - 265,000; Full time

Benefits offered by this job

Pre-IPO stock options

Flexible hours

Medical, dental and vision insurance

Job summary

Ethernovia, Inc. seeks a visionary Principal IC Package Design Engineer to lead architecture and execution of advanced packaging for next-gen Ethernet switches and PHYs.

You will own the package lifecycle from feasibility to mass production, collaborating with Silicon Design, Systems/PCB, and OSAT vendors. The role demands deep expertise in Flip-Chip BGA, SiP, and multi-chip modules, plus strong leadership and communication skills to drive cross-functional programs in a fast-growing hardware

Qualifications

• Bachelor of Science in EE/Materials/Mech or related field.
• 10+ years in IC package design and architecture.
• Experience with high-speed networking or automotive electronics preferred.

Responsibilities

• Package Architecture & Feasibility: Define concepts, stack-ups, bump maps, and pinouts for cost, electrical performance and thermal constraints.
• Detailed Package Design: Execute complex, high-speed multilayer layouts (FCBGA, FCCSP, SiP).
• SI/PI & Thermal Co-Design: Collaborate to meet high-speed SerDes, PDN and thermal targets.
• Substrate Design Integration: Define rules and manage layout, routing, manufacturing constraints.
• OSAT & Vendor Management: Engage with substrates and OSATs during NPI and production ramp.
• Cross-Functional Collaboration: Bridge Silicon IC Design and System/PCB teams for co-design.
• Technology Roadmap: Stay ahead on packaging trends to influence hardware roadmap.

Skills

Advanced Packaging

FCBGA

SiP

MCM

PDN/PI

Thermal management

Leadership

Education

B.S. in Electrical Engineering, Materials Science, Mechanical Engineering, or a related field

Tools

Cadence Allegro APD

SiP Layout

Synopsys 3DIC Compiler

Job description

Ethernovia is developing the future of Ethernet-based networks to realize the full potential of software-defined and autonomous vehicles, robotics and other intelligent machines. Founded in 2018, the company’s breakthrough data transport and acceleration technology is ushering in a new era of connectivity and capabilities in the vehicle and at the edge, including highly reliable autonomy, over-the-air servicing and AI-backed applications.

Ethernovia's co-founders are serial technology entrepreneurs with multiple prior successful ventures together. We are well-funded and backed by some of the worlds’ leading technology investors, having secured $154M ($90+M Series-B and $64M Series-A) in total funding to date:

• (financial backers include: Porsche SE, Qualcomm, AMD, Western Digital, Maverick Silicon, Socratic Partners, Conduit Capital, and CDIB-TEN Capital)

Ethernovia has been recognized in EE Times' prestigious list of the Top 100 Startups for 2025.

With talented employees on 4 continents, we have filed 50+ patents to date.

Join Ethernovia’s team to make a lasting impact on the future of packet processor-centric networking solutions to support the real-time sensor, Physical AI, and control data demands of software-defined autonomy across vehicles, robots and intelligent machines. Come share in our success with pre-IPO shares, competitive compensation, and great benefits while growing your knowledge and career with world class talent. We are looking for talented engineers and leaders who have an entrepreneurial spirit and want to drive cutting edge designs from concept to silicon to the future of mobility.

Principal IC Package Design Engineer

Summary:

We are seeking a visionary and deeply technicalPrincipal IC Package Design Engineerto lead the architecture, design, and execution of advanced packaging solutions for our next-generation Ethernet switches and PHYs. You will be responsible for the entire package lifecycle—from early-stage feasibility and architectural definition to detailed layout, signal/power integrity (SI/PI) co-design, thermal management, and mass production release.

This role requires a blend of deep technical expertise in advanced packaging technologies (e.g., Flip-Chip BGA, high-density substrates) and the leadership capability to collaborate across Silicon Design, Systems/PCB, Reliability, and external OSAT vendors.

Key Responsibilities

• Package Architecture & Feasibility:Lead the definition of package concepts, substrate stack-ups, bump/ball maps, and pinouts to optimize for system cost, electrical performance, and thermal constraints.
• Detailed Package Design:Execute complex, high-speed, multi-layer package layouts (FCBGA, FCCSP, SiP) utilizing industry-standard EDA tools.
• SI/PI & Thermal Co-Design:Partner closely with Signal/Power Integrity and Thermal engineers to ensure package designs meet stringent targets for high-speed SerDes (56G/112G+), power delivery networks (PDN), and thermal dissipation.
• Substrate Design Integration:Define design rules and manage substrate layout, routing optimization, and manufacturing constraints (DFM/DFA).
• OSAT & Vendor Management:Drive technical engagements with leading substrate suppliers and OSATs. Evaluate vendor capabilities, negotiate design rules, and resolve manufacturing/assembly issues during NPI (New Product Introduction) and production ramp.
• Cross-Functional Collaboration:Act as the bridge between Silicon IC Design and System/PCB teams to ensure seamless chip-package-board co-design and optimization.
• Technology Roadmap:Stay at the forefront of semiconductor packaging trends (e.g., advanced organic substrates, glass substrates, co-packaged optics) to influence Ethernovia’s long-term hardware roadmap.

Qualifications & Skills

Required Experience:

• Education:B.S. in Electrical Engineering, Materials Science, Mechanical Engineering, or a related field.
• 10+ years of direct experiencein IC package design and architecture, ideally within high-speed networking, automotive electronics, or high-performance computing (HPC).

Technical Expertise:

• Advanced Packaging:Proven track record of delivering high-volume, complex Flip-Chip BGA (FCBGA), System-in-Package (SiP), and multi-chip module (MCM) designs.
• EDA Tools:Expert proficiency in package design suites such asCadence Allegro Package Designer (APD),SiP Layout, orSynopsys 3DIC Compiler.
• Signal & Power Integrity Foundations:Strong understanding of electromagnetic theory, transmission lines, crosstalk, and PDN concepts. Familiarity with extraction tools (Ansys HFSS/Q3D, Cadence Clarity) is highly desirable.
• Manufacturing Knowledge:Deep understanding of substrate fabrication processes, assembly line limits, and automotive-grade reliability standards (e.g., AEC-Q100 guidelines).

Leadership & Soft Skills:

• Strong problem-solving abilities with a data-driven approach to architectural trade-offs (e.g., performance vs. cost vs. yield).
• Excellent communication skills, with the ability to articulate complex packaging constraints to cross-functional executives and external partners.

What You Can Expect From Ethernovia:

• Technology depth and breadth expansion that can’t be found in a large company
• Opportunity to grow your career as the company grows
• Pre IPO stock options
• Cutting edge technology
• World class team
• Flexible hours
• Medical, dental and vision insurance for employees

Salary Range:

• The actual offered base salary for U.S. locations will vary depending on factors such as work location, individual qualifications, specializations, years of experience, skills, job-related knowledge, and internal equity. The annual salary range for this position is $200,000 - $265,000. The compensation package will also include incentive compensation in the form of pre-IPO ISO options, in addition to base salary and a full range of medical and other benefits.

* Principals Only (No Agencies)