Principal Silicon Design Engineer

191 Altera Corporation; San Jose (CA); On-site; USD 210,000 - 303,000; Full time

Job summary

Altera Corporation in San Jose, CA seeks a Principal High-Speed Interface / Silicon Design Engineer to lead architecture, RTL design, verification, and silicon IP for next-generation FPGA devices. You will own PCIe and related high-speed interfaces, guiding cross-functional teams from architecture through validation.

The role requires deep hands-on RTL with Verilog/SystemVerilog, experience with PAM4/FFE/DFE, PHY/PCS integration, and mentoring of engineers.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• 12+ years of experience in ASIC, SoC, FPGA, silicon, or digital IC design.
• 8+ years of experience designing and developing high-speed interface IP or digital subsystems, including RTL in Verilog/SystemVerilog.
• 5+ years of experience with PCI Express, PCIe PHY/PCS, MAC, Link, or related high-speed serial interfaces.
• 3+ years of experience architecting or leading complex silicon IP or subsystem designs.
• 3+ years of experience with high-speed interfaces such as MIPI/MPHY, HDMI, USB, DisplayPort, or similar.
• 3+ years of experience with digital implementation and signoff methodologies (lint, CDC, synthesis, STA, ECD).
• 3+ years of experience with PAM4/FFE/DFE/CDR/LMS and related equalization techniques.

Responsibilities

• Lead the architecture and RTL design of complex high-speed interface IP, focusing on PCIe and related serial tech.
• Provide technical leadership for current and future high-speed interface architectures.
• Define and develop PCIe MAC, PCS, link, and subsystem functionality and control logic.
• Drive end-to-end ownership from architecture through silicon validation.
• Collaborate with PHY designers on requirements, calibration, and system performance.
• Lead design activities involving high-speed equalization and signal processing techniques.
• Address CDC, lint, synthesis, STA, and formal verification issues with teams.
• Work with verification teams to define strategies and drive silicon validation activities.
• Serve as an interface between digital design, PHY/analog, verification, and product engineering.
• Mentor engineers and provide technical direction on architecture and RTL design.
• Lead technical design reviews and influence multi-team decisions.
• Promote continuous improvements in high-speed design methodologies.

Skills

PCI Express

High-speed interfaces

RTL development

Architecture ownership

Mentorship

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Tools

Verilog/SystemVerilog

SVA/JasperGold

MATLAB/Simulink

FPGA prototyping

Job description

About the Role

Altera is seeking a Principal High-Speed Interface / Silicon Design Engineer to lead the architecture, design, integration, and verification of advanced high-speed interface IP for next-generation FPGA devices. In this role, you will serve as a senior technical authority for high-speed digital interfaces and silicon design, working across architecture, RTL design, verification, PHY/PCS integration, and system-level implementation. The ideal candidate brings deep expertise in PCI Express and other high-speed serial interfaces, with hands-on experience developing complex RTL and silicon IP from architecture through implementation and validation. Experience with PCIe, PHY/PCS, MIPI/MPHY, HDMI, USB/DisplayPort, high-speed equalization, and PAM4 technologies is highly valued. This role will partner closely with architecture, analog/PHY, verification, FPGA, software, and system teams to deliver robust, high-performance interface solutions for Altera's next-generation FPGA platforms.

Responsibilities

• Lead the architecture and RTL design of complex high-speed interface IP and subsystems, with a primary focus on PCIe and related high-speed serial technologies.
• Provide technical leadership for all current and future-generation high-speed interface architectures, including emerging high-bandwidth serial technologies.
• Define and develop PCIe MAC, PCS, link, and subsystem functionality, including high-speed interface protocols, link initialization, equalization, lane management, and related control logic.
• Drive end-to-end technical ownership of high-speed interface designs from architecture and microarchitecture through RTL implementation, verification, synthesis, timing analysis, and silicon validation.
• Develop and integrate high-speed digital interfaces with PHY and analog IP, collaborating closely with PHY designers on interface requirements, calibration, equalization, and system-level performance.
• Lead design activities involving high-speed equalization and signal-processing techniques, including Tx FFE, Rx FFE, CDR, DFE, LMS, and related equalization methodologies.
• Analyze and resolve complex design issues involving CDC, lint, synthesis, STA, formal verification, RTL quality, and subsystem integration.
• Collaborate with verification teams to define verification strategies and drive functional, formal, simulation, FPGA, testchip, and silicon validation activities.
• Serve as a technical interface between digital design, PHY/analog, verification, architecture, software, and product engineering teams.
• Mentor senior and junior engineers and provide technical direction on architecture, RTL design methodology, design reviews, and problem resolution.
• Lead technical design reviews and influence architecture and implementation decisions across multiple engineering teams.
• Drive continuous improvements in high-speed interface design methodologies, verification strategies, and IP reuse.

Salary Range

The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$209,500 - $303,250 USD

We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.

Qualifications

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• 12+ years of experience in ASIC, SoC, FPGA, silicon, or digital IC design.
• 8+ years of experience designing and developing high-speed interface IP or digital subsystems, including hands-on RTL development using Verilog and/or SystemVerilog.
• 5+ years of experience with PCI Express, PCIe PHY/PCS, MAC, Link, or related high-speed serial interface technologies.
• 3+ years of experience architecting or leading complex silicon IP or subsystem designs through multiple stages of the development lifecycle.
• 3+ years of experience working with high-speed interface technologies such as MIPI/MPHY, HDMI, USB, DisplayPort, or comparable serial interfaces.
• 3+ years of experience with digital implementation and signoff methodologies, including lint, CDC, synthesis, static timing analysis, and/or equivalence checking.
• Experience with high-speed equalization or signal-processing techniques, including technologies such as PAM4, FFE, DFE, CDR, LMS, or related methodologies.
• Experience providing technical leadership, architecture ownership, design reviews, and mentorship for complex engineering projects.

Preferred Qualifications

• Master's degree or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• Experience with PCIe Gen5/Gen6 or higher-speed PCIe architectures.
• Experience with PAM4-based high-speed interfaces and digital signal-processing implementations.
• Experience integrating digital logic with analog PHY IP, including PLL, CDR, DFE, equalization, and related circuitry.
• Experience with MATLAB/Simulink or equivalent modeling environments for high-speed interface analysis and verification.
• Experience with formal verification and SVA, including tools such as JasperGold.
• Experience with FPGA-based prototyping, testchip development, post-silicon validation, or ATE.
• Strong understanding of high-speed interface protocols, link training, lane management, equalization, and PHY/PCS architectures.
• Demonstrated ability to lead highly complex technical programs involving multiple engineering disciplines.

Job Type

Regular Shift: Shift 1 (United States of America) Primary Location: San Jose, California, United States Additional Locations:

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

About Altera

Altera: Accelerating Innovators Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.