Principal Formal Verification Engineer — Prove CPU Correctness

NUVACORE; Austin (TX); On-site; USD 140,000 - 210,000; Full time

Job summary

NUVACORE is seeking Formal Verification Engineers at multiple levels to prove the correctness of its next-generation high-performance CPU using formal methods. You will convert micro-architecture specs into proving properties and build verification environments to exhaustively validate designs.

Roles span Senior Engineer to Principal, requiring deep experience in formal verification, model checking, and debugging counterexamples in collaboration with the design team.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering, Computer Science, or Mathematics.
• 4+ years (Senior Engineer) or 15+ years (Principal) of design-verification experience with hands-on formal verification.
• Hands-on formal techniques — model checking and/or equivalence checking — through to proof convergence.
• Strong Verilog/SystemVerilog and assertions/temporal logic.
• Strong knowledge of CPU micro-architecture and digital logic.
• Strong scripting (Python; TCL/Perl a plus), analytical, and debug skills.

Responsibilities

• Plan & Strategy: Drive the verification scope and formal test plan for each verification problem — turning the micro-architecture specification into the properties to prove.
• Formal Environment: Build the formal environment — assumptions, constraints, assertions, and cover properties — plus reusable, optimized formal models.
• Proof & Bug Hunting: Apply model checking, equivalence checking, and abstraction to reach full or bounded proofs, and hunt deep bugs in areas such as cache coherence, memory consistency, and speculative execution.
• Debug & Design Feedback: Debug counterexamples to root cause and partner directly with designers to fix and improve the micro-architecture.
• Flow & Automation: Build and maintain the end-to-end formal flow — automation (Python/TCL), assertion libraries shared across formal and simulation, and tool-issue resolution with vendors.
• Cross-functional Collaboration: Review formal setups and proofs with the design team, and partner closely across the DV team.

Skills

Verilog/SystemVerilog

Model Checking

Equivalence Checking

Python

TCL/Perl

Assertions/Temporal Logic

CPU Micro-architecture

Education

Bachelor's degree in Electrical/Computer Engineering, Computer Science, or Mathematics

Tools

Cadence JasperGold

Synopsys VC Formal

Siemens Questa Formal

Job description

NUVACORE is seeking Formal Verification Engineers at multiple levels to prove the correctness of its next-generation high-performance CPU using formal methods. You will convert micro-architecture specs into proving properties and build verification environments to exhaustively validate designs.

Roles span Senior Engineer to Principal, requiring deep experience in formal verification, model checking, and debugging counterexamples in collaboration with the design team.