Formal Verification Engineer

NUVACORE, Inc.; Town of Texas, Northern (WI, KY); Hybrid; USD 140,000 - 230,000; Full time

Job summary

Nuvacore is building a ground-up high performance, low-power CPU for next-generation compute workloads. We are seeking Formal Verification Engineers at multiple levels—from Senior to Principal—to prove the CPU correct with formal methods, working with the DV team on properties, environments, and proofs.

Responsibilities include driving verification scope, building formal environments, conducting proofs, debugging counterexamples with designers, and automating the end-to-end formal flow using

Qualifications

• Degree in Electrical/Computer Engineering, Computer Science, or Mathematics, or equivalent practical experience.
• 15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience with hands-on formal verification.
• Hands-on formal techniques—model checking and/or equivalence checking—through to proof convergence.
• Strong Verilog/SystemVerilog and assertions/temporal logic.
• Strong knowledge of CPU micro-architecture and digital logic.
• Strong scripting (Python; TCL/Perl a plus), analytical, and debugging skills.

Responsibilities

• Plan & Strategy: Drive the verification scope and formal test plan for each problem.
• Formal Environment: Build assumptions, constraints, assertions, and cover properties.
• Proof & Bug Hunting: Apply model checking, equivalence checking, and abstraction to prove correctness.
• Debug & Design Feedback: Debug counterexamples and collaborate with designers to fix issues.
• Flow & Automation: Build end-to-end formal flow and shared assertion libraries.
• Cross-functional Collaboration: Review formal setups and proofs with the design team.

Skills

Formal verification

Model checking

Equivalence checking

Verilog/SystemVerilog

Python scripting

Debugging

CPU architecture

Temporal logic

Education

Bachelor's degree in Electrical/Computer Engineering, CS, or Mathematics

Tools

Cadence JasperGold

Synopsys VC Formal

Siemens Questa Formal

Job description

Nuvacore is building a ground-up high performance, low-power CPU for next-generation compute workloads. We are seeking Formal Verification Engineers at multiple levels — from Senior Engineer to Principal level — to help prove the Nuvacore CPU correct with formal methods. As part of the design verification (DV) team, you will turn micro-architecture specifications into properties, build the environments to prove them, and use model checking and equivalence checking to exhaustively hunt deep, corner-case bugs — establishing correctness long before silicon, working shoulder-to-shoulder with the design team.

THE ROLE

Plan & Strategy: Drive the verification scope and formal test plan for each verification problem — turning the micro-architecture specification into the properties to prove.

Formal Environment: Build the formal environment — assumptions, constraints, assertions, and cover properties — plus reusable, optimized formal models.

Proof & Bug Hunting: Apply model checking, equivalence checking, and abstraction to reach full or bounded proofs, and hunt deep bugs in areas such as cache coherence, memory consistency, and speculative execution.

Debug & Design Feedback: Debug counterexamples to root cause and partner directly with designers to fix and improve the micro-architecture.

Flow & Automation: Build and maintain the end-to-end formal flow — automation (Python/TCL), assertion libraries shared across formal and simulation, and tool-issue resolution with vendors.

Cross-functional Collaboration: Review formal setups and proofs with the design team, and partner closely across the DV team.

REQUIREMENTS — MUST HAVE

Degree in Electrical/Computer Engineering, Computer Science, or Mathematics, or equivalent practical experience.

15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience, with hands-on formal verification.

Hands-on formal techniques — model checking and/or equivalence checking — through to proof convergence.

Strong Verilog/SystemVerilog and assertions / temporal logic.

Strong knowledge of CPU micro-architecture and digital logic.

Strong scripting (Python; TCL/Perl a plus), analytical, and debug skills.

REQUIREMENTS — NICE TO HAVE

Proficiency with industry formal tools (e.g. Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal).

Taking complex verification problems to proof closure — abstraction, bounded-proof management, and equivalence checking (LEC/SEC) against golden references.

Formal verification of CPU domains such as cache coherence, memory consistency, speculative execution, or data path.

Security formal verification or theorem proving.

Understanding of how formal complements dynamic simulation, and shared assertion libraries.

Mentoring engineers and collaborating across distributed teams.