Formal Verification Engineer

Nuvacore; Austin (TX); On-site; USD 140,000 - 250,000; Full time

Job summary

Nuvacore is seeking Formal Verification Engineers at multiple levels to help validate a high-performance CPU using formal methods. You will translate micro-architecture specs into verifiable properties and build environments to prove them, working closely with the DV team.

Responsibilities include planning verification scope, creating formal models, and performing proof convergence with model and equivalence checking. Strong scripting and debugging skills are essential.

Qualifications

• Hands-on formal verification experience with model checking and/or equivalence checking.
• Experience with CPU micro-architecture concepts and digital logic.
• Proficiency in Verilog/SystemVerilog and temporal logic concepts.

Responsibilities

• Plan & Strategy: define verification scope and formal test plan for each problem.
• Formal Environment: build assumptions, constraints, assertions, and cover properties.
• Proof & Bug Hunting: employ model checking, equivalence checking, and abstraction to reach proofs.
• Debug & Design Feedback: diagnose counterexamples and work with designers to fix issues.
• Flow & Automation: create end-to-end formal flow, scripts, and reusable models.
• Cross-functional Collaboration: review formal setups with DV team.

Skills

Verilog/SystemVerilog

Assertions/temporal logic

Python scripting

Debug & analytical

CPU micro-architecture

Education

B.S. in Electrical/Computer Engineering / CS / Mathematics

Tools

Cadence JasperGold

Synopsys VC Formal

Questa Formal

Job description

Nuvacore is building a ground-up high performance, low-power CPU for next-generation compute workloads. We are seeking Formal Verification Engineers at multiple levels — from Senior Engineer to Principal level — to help prove the Nuvacore CPU correct with formal methods. As part of the design verification (DV) team, you will turn micro-architecture specifications into properties, build the environments to prove them, and use model checking and equivalence checking to exhaustively hunt deep, corner-case bugs — establishing correctness long before silicon, working shoulder-to-shoulder with the design team.

THE ROLE

• Plan & Strategy: Drive the verification scope and formal test plan for each verification problem — turning the micro-architecture specification into the properties to prove.

• Formal Environment: Build the formal environment — assumptions, constraints, assertions, and cover properties — plus reusable, optimized formal models.

• Proof & Bug Hunting: Apply model checking, equivalence checking, and abstraction to reach full or bounded proofs, and hunt deep bugs in areas such as cache coherence, memory consistency, and speculative execution.

• Debug & Design Feedback: Debug counterexamples to root cause and partner directly with designers to fix and improve the micro-architecture.

• Flow & Automation: Build and maintain the end-to-end formal flow — automation (Python/TCL), assertion libraries shared across formal and simulation, and tool-issue resolution with vendors.

• Cross-functional Collaboration: Review formal setups and proofs with the design team, and partner closely across the DV team.

REQUIREMENTS — MUST HAVE

• Degree in Electrical/Computer Engineering, Computer Science, or Mathematics, or equivalent practical experience.

• 15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience, with hands-on formal verification.

• Hands-on formal techniques — model checking and/or equivalence checking — through to proof convergence.

• Strong Verilog/SystemVerilog and assertions / temporal logic.

• Strong knowledge of CPU micro-architecture and digital logic.

• Strong scripting (Python; TCL/Perl a plus), analytical, and debug skills.

REQUIREMENTS — NICE TO HAVE

• Proficiency with industry formal tools (e.g. Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal).

• Taking complex verification problems to proof closure — abstraction, bounded-proof management, and equivalence checking (LEC/SEC) against golden references.

• Formal verification of CPU domains such as cache coherence, memory consistency, speculative execution, or data path.

• Security formal verification or theorem proving.

• Understanding of how formal complements dynamic simulation, and shared assertion libraries.

• Mentoring engineers and collaborating across distributed teams.

$140,000 - $250,000 a year