Principal Engineer, Standard Cell Design (Hybrid)

Intel Corporation; Phoenix (AZ); Hybrid; USD 221,000 - 312,000; Full time

Job summary

Intel Corporation is seeking a Principal Engineer to architect and optimize standard cell libraries for high-performance, low‑voltage operation. You will shape library strategy, drive circuit innovations, and lead cross‑functional collaboration with DTCO, EDA partners, and product teams in the US.

Mentoring junior engineers and advancing methodology will be key. This role supports Intel Foundry and demands strong leadership across CPU/SoC contexts.

Qualifications

• Ph.D. or Master’s degree required.
• 10+ years of industry experience with foundation IP design, DTCO & advanced semiconductor technology.
• Deep MOSFET physics and device-level understanding required.
• Experience with standard cell development and topology choices.
• Ability to lead cross-functional teams and communicate findings clearly.

Responsibilities

• Shape standard cell library strategy, including content definition and ecosystem usability.
• Drive circuit innovation for high-performance and low-voltage operation in sequential/clocking circuits.
• Lead PPA and Vmin optimization across performance, power, and area tradeoffs.
• Coordinate with DTCO, product design teams, and EDA partners to align scalable solutions.
• Mentor circuit designers and raise design quality and methodology across teams.
• Develop and refine circuit methodology, naming conventions, modeling approaches, and validation frameworks.

Skills

MOSFET physics

Transistor-level design

Standard cell development

PPA optimization

Low-power techniques

Clocking/sequential elements

Data analysis & communication

Mentoring junior engineers

Cross-functional collaboration

SPICE simulations

EDA tools

Education

Ph.D. or Master’s degree

10+ years in foundation IP design

Tools

Spice simulation tools

EDA tools

Job description

Intel Corporation is seeking a Principal Engineer to architect and optimize standard cell libraries for high-performance, low‑voltage operation. You will shape library strategy, drive circuit innovations, and lead cross‑functional collaboration with DTCO, EDA partners, and product teams in the US.

Mentoring junior engineers and advancing methodology will be key. This role supports Intel Foundry and demands strong leadership across CPU/SoC contexts.