Principal Architect, Data Center AI CPU Performance

Samsung-Semiconductor; San Jose (CA); On-site; USD 219,000 - 351,000; Full time

Benefits offered by this job

Paid time off

Fertility care stipend

Medical travel support

401k plan

Job summary

Samsung Semiconductor in San Jose, CA invites a Principal Engineer to lead architecture and performance research for data center and agentic AI CPUs. You will shape architectural direction, drive performance modeling, and collaborate with RTL teams to turn ideas into silicon.

The role demands a strong track record in CPU microarchitecture, proficiency in C/C++ and Python, and experience with simulation tools like gem5. Mentorship and cross-team leadership are key.

Qualifications

• Master’s in CE/CS or related field, or PhD with extensive relevant experience.
• 5+ years in CPU microarchitecture or performance engineering.
• Expertise with RISC-V, ARM, or x86 cores.
• Strong quantitative performance analysis and modeling skills.
• Proficiency in C/C++ and Python; RTL/gem5 experience.

Responsibilities

• Define architectural vision for next-gen CPUs and workloads.
• Lead end-to-end performance analysis using simulators and RTL.
• Translate workload insights into architectural requirements.
• Drive alignment from design to silicon and implementations.
• Mentor engineers and contribute to patents/publications.

Skills

CPU microarchitecture

Architecture research

Performance engineering

RISC-V cores

ARM cores

x86 cores

Quantitative analysis

Performance modeling

RTL implementation

C/C++

Python

Education

Master’s degree in Computer Engineering, Computer Science, or a related field

PhD with 15+ years of relevant experience

Tools

gem5

Job description

Samsung Semiconductor in San Jose, CA invites a Principal Engineer to lead architecture and performance research for data center and agentic AI CPUs. You will shape architectural direction, drive performance modeling, and collaborate with RTL teams to turn ideas into silicon.

The role demands a strong track record in CPU microarchitecture, proficiency in C/C++ and Python, and experience with simulation tools like gem5. Mentorship and cross-team leadership are key.