Principal EDA Software Engineer (C++, Characterization)

Cadence Design Systems; San Jose (CA); On-site; USD 137,000 - 254,000; Full time

Benefits offered by this job

Paid vacation

401(k) plan with employer match

Employee stock purchase plan

Medical, dental and vision plans

Job summary

Cadence Design Systems in California is seeking an experienced senior software engineer to advance transistor-level timing analysis tools. You will extend architecture, build new frameworks for detailed analysis, and apply machine learning to boost speed and usability across the existing suite.

The role requires deep C++ expertise on Linux, strong data-structures and algorithms skills, and a BS in CS/EE/CE. Competitive compensation and comprehensive benefits are offered.

Qualifications

• BS degree in Computer Science, Electrical Engineering, or Computer Engineering preferred.
• 8+ years in development of EDA tools with transistor-level timing, power, noise, aging, reliability, or EMIR analysis.
• Hardcore C++ knowledge in a Linux environment and strong data-structures/algorithms skills.
• Experience building and maintaining C++-based applications on Unix/Linux platforms.
• Experience with software quality processes and design thinking.

Responsibilities

• Enhance and expand existing tools' architecture to cover timing analysis.
• Create new frameworks for analyzing effects dominant at n5 and below.
• Leverage machine learning technology to achieve significant improvements in speed, capacity, and usability over existing solutions.

Skills

C++

Linux

Data structures

Algorithms

Software engineering

EDA tools

Education

BS in CS/EE/CE

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Join our expert R&D team as we create technologies and products that enable static and dynamic transistor-level analysis of the most advanced custom digital and mixed-signal circuits, powering the communication, IoT, and AI markets.

Key Responsibilities

• Enhance and expand existing tools' architecture to cover timing analysis.
• Create new frameworks for analyzing effects dominant at n5 and below.
• Leverage machine learning technology to achieve significant improvements in speed, capacity, and usability over existing solutions.

Must-Have Qualifications

• 8+ years of experience in development of EDA tools and expertise in one or more areas: transistor-level timing, power, noise, aging, reliability, and EMIR analysis.
• Hardcore C++ knowledge, particularly in a Linux environment.
• Strong proficiency in designing data structures, algorithms, and applying software engineering principles.
• Industry experience developing and maintaining C++ based applications on Unix or Linux platforms.
• Requirements Experience with quality and software processes.
• Proficiency in designing data structures, algorithms, and software engineering principles.
• Ability to analyze transistor or gate-level schematics.
• BS degree in Computer Science, Electrical Engineering, or Computer Engineering preferred.

Nice-to-Have Skills

• Experience in development of circuit simulation or library characterization programs.
• Understanding of SPICE simulation transistor models at a high level.
• Experience with distributed programming, database design, and cloud APIs for distributed computing.

Why Cadence?

At Cadence, you’ll work alongside industry leaders and innovators who are passionate about advancing technology. Your contributions will directly impact the development of cutting-edge tools and solutions for the communication, IoT, and AI industries. We foster a collaborative environment where your expertise and ideas will shape the technology of tomorrow.

The annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.

Benefits

• paid vacation and paid holidays
• 401(k) plan with employer match
• employee stock purchase plan
• a variety of medical, dental and vision plan options

Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization.

We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact [e-mail].

Cadence participates in the E-Verify program in certain U.S. locations as required by law. Cadence plays a critical role in creating the technologies that modern life depends on.

Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.