Principal Digital Design Engineer — GaN/SiC PMIC Innovations

Navitas Semiconductor Usa; Torrance (CA); In loco; USD 170.000 - 190.000; Tempo pieno

Vantaggi offerti da questo lavoro

Health insurance

Equity awards

Unlimited PTO

Competitive compensation

Descrizione del lavoro

Navitas Semiconductor USA in Torrance, CA seeks a Principal Digital Design Engineer to design and verify digital blocks for GaNFast PMICs. You will run pre-silicon simulations, build UVM testbenches, and drive coverage closure across multiple projects.

The role requires strong SystemVerilog expertise, familiarity with Cadence tools, and hands-on FPGA prototyping for silicon validation. Leadership and mentoring are expected within a fast-paced environment.

Competenze

• B.S. in Electrical Engineering or related field required.
• 5+ years in digital hardware design (ASIC/FPGA/embedded).
• Strong SystemVerilog experience for design and verification.
• Solid understanding of RTL, synthesis, timing, and verification.
• Experience with digital simulation tools (Xcelium, Questa, Vivado).
• FPGA prototyping with Xilinx tools for silicon validation.

Mansioni

• Design and implement digital blocks for ASICs using Verilog/SystemVerilog.
• Conduct pre-silicon simulation and verification with Cadence tools.
• Develop and maintain UVM/SystemVerilog testbenches with coverage models.
• Own coverage closure and improve verification suites.
• Apply formal verification methods where applicable (property checking).
• Lead post-silicon debug and feed learnings back into design and verification.
• Collaborate with analog/design teams to ensure robust PMIC design.

Conoscenze

Verilog/SystemVerilog

UVM/SystemVerilog

Digital design

Scripting

Cadence tools

Formazione

B.S. Electrical Engineering

M.S./PhD preferred

Strumenti

Cadence Xcelium

Genus

Conformal

Modus

Tempus/Innovus

Vivado

Descrizione del lavoro

Navitas Semiconductor USA in Torrance, CA seeks a Principal Digital Design Engineer to design and verify digital blocks for GaNFast PMICs. You will run pre-silicon simulations, build UVM testbenches, and drive coverage closure across multiple projects.

The role requires strong SystemVerilog expertise, familiarity with Cadence tools, and hands-on FPGA prototyping for silicon validation. Leadership and mentoring are expected within a fast-paced environment.