Principal Digital Design Engineer

Hardware FYI

San Jose, Northern (CA, KY)

Hybrid

USD 185,000 - 240,000

Full time

6 days ago
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Job summary

Astera Labs is seeking a Principal Digital Design Engineer in the United States to lead front-end circuit design, RTL, and verification for high‑performance network controllers. You will own architecture‑to‑GDSII delivery and work with teams to meet tight timing on advanced CMOS processes.

The role requires hands‑on experience with PCIe, ULink, Esun, Ethernet, and strong front‑end design, verification, and test expertise. UVM familiarity and US work authorization are preferred.

Qualifications

  • Bachelor's degree in Electrical Engineering required; Master's preferred.
  • +8 years’ experience in complex SoC/silicon products for Switch ASIC/Networking/Server.
  • Experience with front-end design, RTL, verification, timing, and DFT.
  • Proficiency with high-speed protocols (PCIe, Ualink, Esun, Ethernet).

Responsibilities

  • Lead front-end design from architecture to GDS, delivering complex designs to production.
  • Perform RTL, simulations, synthesis, and timing closure.
  • Drive design-for-test and UVM-based verification.
  • Collaborate with cross-functional teams and customers to meet requirements.

Skills

Front-end design
RTL
Synthesis
DFT
UVM
Timing closure
PCIe
ULink
Hardware verification
Silicon bring-up

Education

Bachelor's degree in EE
Master's degree

Tools

Synopsys tools
Cadence tools

Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Job Description

We are looking for Principal Digital Design Engineers with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers. The candidate must have good knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ualink, Esun, Ethernet etc.

Basic Qualifications:
  • Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE is required, and a Master’s degree is preferred.
  • +8 years’ experience supporting or developing complex SoC/silicon products for Switch ASIC, Networking applications and/or Server, Storage.
  • Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
  • Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
  • Authorized to work in the US and start immediately.
Required Experience:
  • Hands-on, thorough knowledge of high-speed protocols like PCIe, Ualink, Esun, Ethernet, etc.
  • Proven front end design expertise – architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc.
  • Full chip or block level ownership from architecture to GDS, driving multiple complex designs to production
  • Experience with Synopsys and/or Cadence digital design tools/flows
  • Good knowledge of design for test (DFT), stuck-at and transition scan test insertion
  • Familiarity with UVM based design verification
  • Silicon bring-up and debug expertise
  • Small-geometry CMOS (≤28nm) design
Preferred Experience:
  • Firmware development with C-language, scripting with Python or other equivalent programming languages.
  • Development/support for PCIe or Ethernet Switch products.

The base salary range is $185,000.00 USD – $240,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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