Principal Digital Design Engineer

NXP Semiconductors NV; Chandler (AR); On-site; USD 140,000 - 210,000; Full time

Job summary

NXP Semiconductors N.V. in the United States seeks a senior engineer to lead the digital architecture, design, verification and implementation of PMICs for automotive and industrial applications.

You will drive product execution from concept to RTL development, silicon validation, and production release, collaborating with cross-functional teams to ensure high-quality mixed-signal solutions. The role requires a strong background in RTL design (Verilog/SystemVerilog), advanced verification (UVM,

Qualifications

• MS in Electrical/Computer Engineering required.
• Minimum 12 years of digital IC design and development experience with architecture responsibilities.
• Strong RTL design experience using Verilog/SystemVerilog for complex ICs.
• Experience with synthesis, static timing analysis, and physical implementation flows.
• Proficiency in modern verification methodologies including UVM, assertions, and formal verification.

Responsibilities

• Lead digital architecture, design, verification, and implementation of PMICs for automotive/industrial apps.
• Drive product execution from concept through RTL development, silicon validation and production release.
• Collaborate across analog, verification, validation, and systems teams to deliver mixed-signal solutions.
• Review requirements, IP architectures, and planning for PMIC apps.
• Define and implement digital architectures ensuring alignment with performance, quality and power constraints.
• Lead RTL development, synthesis, timing closure, low-power implementation, silicon bring-up, and release.
• Develop digital control, monitoring, telemetry, protection, and fault management for PMICs.
• Develop RTL/microarchitecture specs using Verilog/SystemVerilog and industry tools.
• Drive verification strategy including test planning, simulation, formal verification, and coverage.

Skills

Digital IC design

RTL design

Verilog/SystemVerilog

UVM

Formal verification

Power management

Low-power design

Clock-domain crossing

Debug and silicon bring-up

Education

M.S. in Electrical Engineering

Electrical or Computer Engineering

Tools

Cadence

Synopsys

Siemens EDA

Job description

Role Summary:

• Lead digital architecture, design, verification, and implementation of next-generation Power Management ICs (PMICs) for automotive and industrial applications.

• Drive product execution from concept through RTL development, integration, silicon validation, qualification, and production release.

• Collaborate across analog, verification, validation, subsystem, SoC, applications, systems, product definition, and customer-facing teams to deliver high-quality mixed-signal solutions.

Job Responsibility:

• Review product requirements, IP architecture specifications, programming models, microarchitecture, interfaces, and implementation plans for automotive and industrial PMIC applications.

• Define and implement digital architectures for mixed-signal PMICs, ensuring alignment with system, performance, quality, reliability, safety, power, and area requirements.

• Lead digital design activities from architecture definition through RTL development, integration, synthesis, timing closure, low-power implementation, silicon bring-up, and production release.

• Design and develop digital control, monitoring, telemetry, diagnostics, configuration, protection, power sequencing, and fault management functions for PMIC and power conversion products.

• Develop and review RTL, microarchitecture, and design specifications using Verilog/SystemVerilog and industry-standard design and quality checking tools.

• Drive verification strategy and execution, including test planning, simulation, formal verification, coverage analysis, regression management, and achievement of NXP quality and maturity standards.

• Deliver complete IP solutions, including RTL, verification collateral, supporting documentation, and requirements traceability from specification through implementation.

• Track development metrics including milestones, code and functional coverage, defect resolution, and compliance with design requirements.

• Support silicon debug, characterization, qualification, reliability validation, and production ramp activities.

• Mentor junior engineers and drive continuous improvement in design methodologies, automation flows, and engineering best practices.

Job Qualification:

• M.S. in Electrical Engineering, Computer Engineering, or a related field required.

• Minimum 12 years of experience in digital IC design and development, including technical leadership and architecture responsibilities.

• Strong understanding of digital design fundamentals, finite state machines, clock-domain crossing, reset architecture, and low-power design techniques.

• Expertise in RTL design using Verilog/SystemVerilog for complex digital and mixed-signal ICs.

• Experience with synthesis, static timing analysis, equivalence checking, DFT, and physical implementation flows.

• Strong knowledge of modern verification methodologies, including UVM, assertions, formal verification, and coverage-driven verification.

• Experience developing digital controllers for PMICs, power management systems, automotive electronics, or industrial applications is highly desirable.

• Proficiency with industry-standard EDA tools from Cadence, Synopsys, and Siemens EDA.

• Strong analytical and problem-solving skills with the ability to develop innovative solutions for complex technical challenges.

• Excellent written and verbal communication skills with proven ability to lead cross-functional teams in a fast-paced product development environment.

More information about NXP in the United States...

NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.