Lead Design Engineer

Cadence Design Systems, Inc.; Austin (TX); On-site; USD 140,000 - 200,000; Full time

Job summary

Cadence Design Systems, Inc. is seeking a Senior DV Engineer in Austin, TX to lead verification strategy and architecture for complex ASIC/SoC designs.

You will design scalable testbenches, BFMs, and coverage-driven plans while guiding junior engineers and collaborating with design, architecture, and emulation teams. You will drive constrained‑random testing, formal verification, and GLS oversight to ensure high functional coverage and timely sign‑off on verification milestones.

Qualifications

• 4–7 years of hands‑on DV experience in semiconductor/ASIC/SoC.
• Bachelor or Master in Electronics or related field.
• Experience with testbench architecture, constrained‑random testing, and formal verification is a plus.

Responsibilities

• Define verification strategy and architecture for the project.
• Design scalable, reusable testbenches with BFMs, monitors, scoreboards, and checkers.
• Lead debugging and root‑cause analysis with design engineers.
• Implement constrained‑random stimulus and formal verification techniques.
• Monitor and analyze functional and code coverage metrics.
• Oversee gate‑level simulations to validate timing and reset behavior.

Skills

UVM.SystemVerilog

Verilog

Testbench development

Education

B.E./B.Tech or M.Tech in Electronics or related field

Tools

UVM/SystemVerilog

Verilog

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Core Responsibilities

• Strategy and Architecture Verification Planning: Define the overall verification strategy, including the choice of methodology (typically UVM/SystemVerilog), tools, and infrastructure.
• Testbench Architecture: Design scalable, reusable, and robust verification environments. This includes developing Bus Functional Models (BFMs), monitors, scoreboards, and checkers.
• Feature Extraction: Analyze architectural specifications to identify critical features and corner cases that require rigorous testing.
• Execution and Technical Leadership Development: Write complex test cases and sequences to achieve high functional coverage.
• Debug: Lead the root-cause analysis of complex design bugs, collaborating closely with design engineers to implement fixes.
• Constraint Random Testing: Implement constrained-random stimulus generation to explore the design space beyond directed tests.
• Formal Verification: Utilize formal tools to prove specific properties or find deep‑seeded bugs that simulation might miss.
• Metric Management Coverage Analysis: Monitor and analyze functional and code coverage metrics.
• Gate‑Level Simulation (GLS): Oversee simulations on the synthesized netlist to verify timing and reset behavior.
• Sign‑off: Define the "definition of done" and provide final technical approval for the verification phase.
• Soft Skills and Leadership Mentorship: Guiding junior engineers on coding standards and debugging techniques.
• Cross‑functional Collaboration: Acting as the primary technical point of contact between the design, architecture, and emulation teams.
• Project Management: Managing timelines, identifying risks in the verification schedule, and prioritizing tasks to meet project deadlines.

Required Qualifications

• B.E./B.Tech or M.Tech/M.S. in Electronics, VLSI, or related field 4–7 years of hands‑on DV experience in semiconductor/ASIC/SoC companies

Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization.

E-Verify Cadence participates in the E-Verify program in certain U.S. locations as required by law.

Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.