Principal Data Center Networking & PCIe Architect

Socket.dev; Sunnyvale (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Health coverage

Unlimited PTO

401(k) matching

Stock options

Voluntary benefits

Job summary

Neurophos in Austin, TX or Sunnyvale, CA seeks a Principal Network Architect to own the datacenter scale-out architecture for our T100 platform. The role covers the path from Linux host networking through PCIe bridges to NICs and back via DMA into HBM.

The candidate will drive RDMA transports, RoCEv2, and UET, while shaping the architectural case for future Neurophos DPUs and scale-up fabric. Strong cross-functional leadership is essential.

Qualifications

• BS/MS/PhD in Computer Science, Electrical Engineering, or a related field.

Responsibilities

• Own the end-to-end scale-out data path architecture spanning host network stack, EIC PCIe bridge, NIC attachment, and DMA into HBM.
• Define the transport and offload architecture, including RoCEv2 and Ultra Ethernet Transport (UET).
• Specify peer-to-peer DMA topology and ACS policy across the PCIe hierarchy.
• Define queue and completion semantics exposed to the runtime, in partnership with the software team.
• Drive NIC vendor selection and own the technical engagement with networking silicon partners.
• Model and evaluate collective communication performance for distributed inference workloads.
• Own the architectural case and roadmap for a future Neurophos DPU and scale-up fabric in a later phase.
• Represent Neurophos in relevant standards bodies and the data center networking community.
• Establish networking architecture practices and mentor engineers across Architecture and Software.

Skills

RDMA transports

Linux networking stack

PCIe mastery

NIC engagement

Networking architecture

Education

BS/MS/PhD in Computer Science or Electrical Engineering

Tools

DPDK

libfabric

VFIO

IOMMU/IOVA

Job description

Neurophos in Austin, TX or Sunnyvale, CA seeks a Principal Network Architect to own the datacenter scale-out architecture for our T100 platform. The role covers the path from Linux host networking through PCIe bridges to NICs and back via DMA into HBM.

The candidate will drive RDMA transports, RoCEv2, and UET, while shaping the architectural case for future Neurophos DPUs and scale-up fabric. Strong cross-functional leadership is essential.