Principal CAD Engineer - EDA Flows & Tapeout Automation

Niuro; Santa Clara (CA); Hybrid; USD 150,000 - 210,000; Full time

Job summary

Niuro in Santa Clara, CA is seeking a Principal CAD Engineer to drive the technical direction for CMOS IC CAD flows, including EDA tool suites and PDK customization. This onsite role emphasizes optimization, performance testing, and tapeout support across multiple sites.

You will interface with major EDA vendors, develop automation scripts, and ensure compliance with foundry quality standards to enhance design efficiency.

Qualifications

• Bachelor's degree or higher in Electrical Engineering, Computer Science, or related field.
• Minimum 8 years of CMOS IC CAD support and new product development experience.
• C2 English level or higher.
• Onsite 5 days a week in Santa Clara, CA.

Responsibilities

• Provide full lifecycle support for custom CAD flows across Cadence, Synopsys, Siemens, and Keysight platforms.
• Own PDK installation, validation, customization, maintenance, and release management.
• Support end-to-end tapeout flows and coordinate tapeout submissions to foundries.
• Develop CAD utilities, automation scripts, and regression flows to improve efficiency.
• Interface with EDA vendors to resolve issues and influence product improvements.
• Provide CAD software and Linux user support for CMOS design and IC layout engineers, including documentation.

Job description

Niuro in Santa Clara, CA is seeking a Principal CAD Engineer to drive the technical direction for CMOS IC CAD flows, including EDA tool suites and PDK customization. This onsite role emphasizes optimization, performance testing, and tapeout support across multiple sites.

You will interface with major EDA vendors, develop automation scripts, and ensure compliance with foundry quality standards to enhance design efficiency.