Principal ATE Test Engineer

Astera Labs; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Flexible time off in the US

Parental leave

401K

Retirement and pension plans

Competitive medical, dental and vision

Job summary

Astera Labs is seeking a Principal ATE Test Engineer to lead ATE programs for complex mixed-signal SoC products. You will define test strategies, drive coordination with manufacturing partners, and own programs from design through high-volume ramp.

You’ll apply your deep knowledge of high-speed protocols (PCIe, Ethernet, DDR, NVMe) and ATE platforms to optimize tester resources while ensuring quality. A strong collaboration with design teams is essential to success.

Qualifications

• Bachelor’s degree in Electrical Engineering required, Master’s preferred.
• Hands-on experience with ATE programming and high-speed test platforms.
• Strong knowledge of high-speed protocols (PCIe, Ethernet, Infiniband, DDR, NVMe, USB).
• Experience releasing complex SoC/silicon products to high volume manufacturing.

Responsibilities

• Develop and oversee SoC test strategy and ATE programs.
• Interact with manufacturing partners to drive high-volume ramp.
• Own test product from design through initial samples to production ramp.
• Collaborate with design teams to define test strategy and plans.
• Implement DFT techniques (SCAN, MEMBIST, SerDes) for coverage.

Skills

Communication skills

Team player

Multitasking

Programming in C/C++/Python

Data processing

Education

Bachelor’s degree in EE

Master’s degree preferred

Tools

Teradyne ATE

Advantest 93k ATE

Oscilloscopes

Protocol analyzers

Job description

• We are looking for Principal ATE Test Engineers with proven experience in developing and supporting complex mixed-signal silicon SoC products to lead ATE Test solutions

Benefits

• Flexible time off in the US
• Parental leave
• 401K
• Retirement and pension plans
• Competitive medical, dental and vision plans

The ideal candidate will develop and oversee SoC test strategy, interact with manufacturing partners, define, and implement ATE programs and own the product from design, initial samples all the way through high volume production rampThe candidate should have working knowledge of communication/interface protocols such as PCI-Express (Gen-4/5/6), Ethernet, Infiniband, DDR, NVMe, USB, etcEntrepreneurial, open-mind behavior and can-do attitudeStrong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Master’s is preferredProfessional attitude with ability to execute on multiple tasks with minimal supervisionWorking knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etcStrong team player with good communication skills to work alongside a team of high caliber engineers

• 8-year experience releasing complex SoC/silicon products to high volume manufacturing
• Hands-on experience with high-speed mixed signal SoC test program/hardware development on multiple high-speed test platforms
• Familiar with high-speed load board design techniques
• Skilled in ATE programming, silicon/ATE bring-up, bench-ATE correlation and debug
• Expertise in production test of high speed SerDes operating at 16Gbps and higher
• Experience with using Teradyne or Advantest 93k ATE platform
• Proven track record of implementing ATE patterns to optimize tester resources and minimize ATE test time while maintaining product quality
• Skilled in control interfaces - I2C, I3C, SPI, MDIO, JTAG etc
• Collaboration with design team to define test strategy, create and own test plan
• Strong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage - SCAN, MEMBIST, SerDes and other functional tests
• Tester platform selection, design, and development of ATE hardware for wafer sort and final test
• Proficiency in, at least, one modern programming language such as C/C++, Python
• Experience with lab equipment including protocol analyzers and oscilloscopes
• Fluent in data processing using high level programming languages
• Experience in running External loopback at wafer sort
• Familiarity with modern databases
• Basic knowledge of RF Testing on ATE Platform