ATE Solution Test Engineer

191 Altera Corporation; San Jose (CA); On-site; USD 118,900 - 172,000; Full time

Job summary

Altera Corporation seeks an ATE Solution Test Engineer to deliver scalable, high‑quality test solutions for wafer sort and final test. You will standardize methodologies and optimize production test across Teradyne and Advantest platforms, shaping test programs from NPI through production ramp.

You will collaborate with Design, DFT, Validation, Reliability, Package Eng, Manufacturing, and OSAT to ensure successful product execution and cost‑effective test.

Qualifications

• Bachelor’s or Master’s degree in Electrical, Computer Engineering, or related field.
• 5+ years developing Automated Test Equipment (ATE) test programs using Teradyne and/or Advantest platforms.
• 5+ years of experience with semiconductor test methodologies, silicon characterization, and production test development for complex semiconductor devices.
• 5+ years of experience developing and implementing ATE test methods for semiconductor products from characterization through high‑volume manufacturing.
• 5+ years of experience working with Design‑for‑Test (DFT) architectures, including Scan, MBIST, JTAG, Boundary Scan, and ATPG.
• 5+ years of experience supporting wafer sort, final test, and semiconductor manufacturing test flows.
• 5+ years of experience working with production test hardware, including probe cards, load boards, sockets, and related ATE interface hardware.
• 5+ years of experience analyzing process variation, optimizing test guardbands, and developing production test limits to improve yield and quality.
• 5+ years of programming or scripting experience using Python, Perl, C++, or similar languages to automate test development, data analysis, or engineering workflows.
• 5+ years of experience using JMP or equivalent statistical data analysis tools for silicon characterization, yield analysis, and test optimization.
• 3+ years of experience working in Agile development environments and using version control systems (e.g., Git).

Responsibilities

• Develop, validate, and maintain ATE test methods and production test programs for wafer sort and final test using Teradyne and/or Advantest platforms.
• Own product test development through the complete product lifecycle—from NPI, silicon bring‑up, characterization, qualification, and production ramp to sustaining engineering.
• Analyze silicon performance across process, voltage, and temperature (PVT) corners to establish production limits and optimize guardbands.
• Drive yield improvement, test time reduction, and defect escape prevention through data‑driven analysis and test optimization.
• Perform silicon, tester, hardware, and manufacturing debug to resolve complex product issues.
• Collaborate with cross‑functional teams including Design, DFT, Validation, Reliability, Package Engineering, Manufacturing, and OSAT partners to ensure successful product execution.
• Support production releases, manufacturing transfers, and high‑volume manufacturing while driving continuous improvements in quality and cost of test.

Skills

Python

Perl

C++

Test automation

Data analysis

JMP

Agile

Git

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Teradyne

Advantest

Probe hardware

Job description

Altera™ is the world’s largest pure‑play FPGA solutions provider, combining four decades of industry‑leading FPGA expertise with a mission to deliver programmable technologies that enable customers to innovate and scale across rapidly evolving markets such as AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely, empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

About the Role

The ATE Solution Test Engineer is responsible for delivering best‑in‑class ATE test solutions that are scalable, high quality, and aligned to product needs. Our mission is to standardize and simplify methodologies and flows, enabling predictable, fast, and consistent Test Program (TP) releases. In addition, we will deliver test hardware designed and optimized for production across all FPGA products.

Responsibilities

• Develop, validate, and maintain ATE test methods and production test programs for wafer sort and final test using Teradyne and/or Advantest platforms.
• Own product test development through the complete product lifecycle—from NPI, silicon bring‑up, characterization, qualification, and production ramp to sustaining engineering.
• Analyze silicon performance across process, voltage, and temperature (PVT) corners to establish production limits and optimize guardbands.
• Drive yield improvement, test time reduction, and defect escape prevention through data‑driven analysis and test optimization.
• Perform silicon, tester, hardware, and manufacturing debug to resolve complex product issues.
• Collaborate with cross‑functional teams including Design, DFT, Validation, Reliability, Package Engineering, Manufacturing, and OSAT partners to ensure successful product execution.
• Support production releases, manufacturing transfers, and high‑volume manufacturing while driving continuous improvements in quality and cost of test.

Qualifications

• Bachelor’s or Master’s degree in Electrical, Computer Engineering, or a related discipline.
• 5+ years of industry experience developing Automated Test Equipment (ATE) test programs using Teradyne and/or Advantest platforms.
• 5+ years of experience with semiconductor test methodologies, silicon characterization, and production test development for complex semiconductor devices.
• 5+ years of experience developing and implementing ATE test methods for semiconductor products from characterization through high‑volume manufacturing.
• 5+ years of experience working with Design‑for‑Test (DFT) architectures, including Scan, MBIST, JTAG, Boundary Scan, and ATPG.
• 5+ years of experience supporting wafer sort, final test, and semiconductor manufacturing test flows.
• 5+ years of experience working with production test hardware, including probe cards, load boards, sockets, and related ATE interface hardware.
• 5+ years of experience analyzing process variation, optimizing test guardbands, and developing production test limits to improve yield and quality.
• 5+ years of programming or scripting experience using Python, Perl, C++, or similar languages to automate test development, data analysis, or engineering workflows.
• 5+ years of experience using JMP or equivalent statistical data analysis tools for silicon characterization, yield analysis, and test optimization.
• 3+ years of experience working in Agile development environments and using version control systems (e.g., Git).

Job Details

Job Type: Regular
Shift: 1 (United States of America)
Primary Location: San Jose, California, United States

Compensation

Salary Range (Bay Area, California Only): $118,900 - $172,000 USD. Incentive opportunities based on individual and company performance.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.