Principal Analog Design Engineer - Photonic AI Hardware

US Health Partners, LLC; Sunnyvale (CA); Hybrid; USD 180,000 - 280,000; Full time

Benefits offered by this job

Health plan coverage

Unlimited PTO

401(k) matching and stock options

Voluntary benefits

Personalized benefits selection

Job summary

Neurophos in San Jose, CA is seeking a seasoned Principal Analog Design Engineer to advance full-custom analog transceiver blocks for our photonics-enabled AI platform. You will own the lifecycle from spec to tape-out in CMOS processes up to GHz speeds.

Collaborate with Photonics and Digital teams across hardware design, layout, and bench testing to push performance, noise, and signal integrity.

Requires 10+ years of experience, Cadence Virtuoso mastery, and proven tape-outs; onsite only.

Qualifications

• MS or PhD in Electrical Engineering.
• 10+ years of full-custom analog IC design experience.
• 5+ years in GHz-speed RF or broadband analog design.
• Cadence Virtuoso proficiency for schematic, simulation and layout.
• Experience taking high-speed analog blocks from concept to mass production (tape-outs).
• Knowledge of CMOS processes, noise, linearity, and signal integrity.

Responsibilities

• Design, simulate, and verify high-speed analog circuits including drivers, TIAs, ADCs/DACs, and PLLs in deep-submicron CMOS technologies.
• Define architecture and specifications for electronic blocks from system-level requirements.
• Perform full-custom schematic capture, analog simulations, and complete physical layout with DRC/LVS using Cadence Virtuoso.
• Ensure signal integrity and power integrity across high-speed interconnects.
• Conduct layout floor planning and post-layout extraction/simulation to validate performance against parasitics.
• Collaborate with Photonics and Digital teams to optimize electro-optic interfaces.
• Prepare and conduct bench characterization and production tests.

Skills

Analog circuit design

Transimpedance amplifiers

Noise analysis

Signal integrity

Photonic transceivers

Tape-out

PLL design

Education

MS/PhD in Electrical Engineering

Tools

Cadence Virtuoso

EM simulation tools (HFSS/EMX)

Spectre RF

TSMC N5P/N3P/N2P experience

Job description

Neurophos in San Jose, CA is seeking a seasoned Principal Analog Design Engineer to advance full-custom analog transceiver blocks for our photonics-enabled AI platform. You will own the lifecycle from spec to tape-out in CMOS processes up to GHz speeds.

Collaborate with Photonics and Digital teams across hardware design, layout, and bench testing to push performance, noise, and signal integrity.

Requires 10+ years of experience, Cadence Virtuoso mastery, and proven tape-outs; onsite only.