Senior Silicon Photonics Analog IC Design Engineer (Hybrid)

Intel; Santa Clara (CA); Híbrido; USD 142.000 - 269.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Stock bonuses

Health benefits

Vacation

Descripción de la vacante

Intel in Santa Clara, CA seeks a Senior Analog Design Engineer to drive high-speed, mixed-signal IC design for silicon photonics and optical interconnects. You will architect, implement, and validate analog blocks, collaborating with digital and design teams to meet power, performance, and reliability goals.

Minimum qualifications include an M.S. in EE with 4+ years of industry experience or PhD with 2+ years, plus hands-on experience with amplifiers, TIAs, PLLs, and data rates above 32 Gbps.

Formación

• M.S. degree in Electrical Engineering or related field with 4+ years of industry experience or PhD with 2+ years in related areas.
• Experience designing high-speed circuit blocks (amplifiers, drivers, TIAs, PLLs) for 32 Gbps and above.
• Strong expertise in high-speed serial link design and analog CMOS/BiCMOS in deep-submicron processes.

Responsabilidades

• Architect, design, implement, and validate high-speed analog and mixed-signal ICs for optical interconnect products.
• Collaborate with cross-functional teams to deliver concepts to production.
• Define architectures and ensure power, performance, and functionality goals are met.
• Lead block-level design and guide multidisciplinary teams through IC development.
• Create and maintain comprehensive design documentation.

Conocimientos

High-speed design

Analog CMOS/BiCMOS

TDMA/PLL concepts

ESD design & verification

Mixed-signal ICs

Educación

M.S. in Electrical Engineering

PhD with 2+ years

Herramientas

Cadence

EM platform tools

Descripción del empleo

Intel in Santa Clara, CA seeks a Senior Analog Design Engineer to drive high-speed, mixed-signal IC design for silicon photonics and optical interconnects. You will architect, implement, and validate analog blocks, collaborating with digital and design teams to meet power, performance, and reliability goals.

Minimum qualifications include an M.S. in EE with 4+ years of industry experience or PhD with 2+ years, plus hands-on experience with amplifiers, TIAs, PLLs, and data rates above 32 Gbps.