Principal Analog Design Engineer

US Health Partners, LLC; Sunnyvale (CA); Hybrid; USD 180,000 - 280,000; Full time

Benefits offered by this job

Health plan coverage

Unlimited PTO

401(k) matching and stock options

Voluntary benefits

Personalized benefits selection

Job summary

Neurophos in San Jose, CA is seeking a seasoned Principal Analog Design Engineer to advance full-custom analog transceiver blocks for our photonics-enabled AI platform. You will own the lifecycle from spec to tape-out in CMOS processes up to GHz speeds.

Collaborate with Photonics and Digital teams across hardware design, layout, and bench testing to push performance, noise, and signal integrity.

Requires 10+ years of experience, Cadence Virtuoso mastery, and proven tape-outs; onsite only.

Qualifications

• MS or PhD in Electrical Engineering.
• 10+ years of full-custom analog IC design experience.
• 5+ years in GHz-speed RF or broadband analog design.
• Cadence Virtuoso proficiency for schematic, simulation and layout.
• Experience taking high-speed analog blocks from concept to mass production (tape-outs).
• Knowledge of CMOS processes, noise, linearity, and signal integrity.

Responsibilities

• Design, simulate, and verify high-speed analog circuits including drivers, TIAs, ADCs/DACs, and PLLs in deep-submicron CMOS technologies.
• Define architecture and specifications for electronic blocks from system-level requirements.
• Perform full-custom schematic capture, analog simulations, and complete physical layout with DRC/LVS using Cadence Virtuoso.
• Ensure signal integrity and power integrity across high-speed interconnects.
• Conduct layout floor planning and post-layout extraction/simulation to validate performance against parasitics.
• Collaborate with Photonics and Digital teams to optimize electro-optic interfaces.
• Prepare and conduct bench characterization and production tests.

Skills

Analog circuit design

Transimpedance amplifiers

Noise analysis

Signal integrity

Photonic transceivers

Tape-out

PLL design

Education

MS/PhD in Electrical Engineering

Tools

Cadence Virtuoso

EM simulation tools (HFSS/EMX)

Spectre RF

TSMC N5P/N3P/N2P experience

Job description

About Neurophos

The demand for new data centers and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck means rethinking the fundamental architecture of inference compute. The industry's current path can't meet the need, so we're taking a different approach.

Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large‑scale AI inference.

We’ve assembled a world‑class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others.

Join us and shape the future of computing!

Position Overview:

We are seeking a seasoned Principal Analog Design Engineer to play a vital role in developing cutting‑edge full‑custom electronic transceiver components that interface directly with our custom silicon photonics and are essential to our revolutionary photonic AI platform. You will be responsible for the full lifecycle of analog blocks, from specification and architecture down to tape‑out‑ready layout. Success in this role requires a deep understanding of transistor‑level circuit design, linearity, noise performance, and signal integrity in CMOS processes up to GHz speeds. If you possess a proven track record of designing robust, ultra‑fast analog circuits and are eager to work at the intersection of electronics and photonics, you will make a defining impact on the future of optical computing.

Location: San Jose, CA or Hsinchu, Taiwan. Full‑time onsite position.

Key Responsibilities:

• Design, simulate, and verify high‑speed analog circuits, including but not limited to high‑swing drivers, transimpedance amplifiers, ADCs, DACs, and PLLs, in deep‑submicron CMOS technologies.

• Define architecture and specifications for electronic blocks based on system‑level requirements.

• Perform full‑custom schematic capture, advanced analog simulations, and complete physical layout, including DRC/LVS, of critical analog blocks using Cadence Virtuoso.

• Ensure rigorous signal integrity and power integrity across all high‑speed interconnects.

• Conduct layout floor planning.

• Conduct post‑layout extraction and simulation to validate performance against parasitic effects.

• Collaborate closely with the Photonics and Digital teams to optimize the electro‑optic interface, maximizing performance across the combination of disciplines.

• Collaborate with team members to prepare and conduct the bench characterization and production tests.

Qualifications:

• MS or PhD in Electrical Engineering.

• 10+ years of professional experience in full‑custom analog integrated circuit design, 5+ years of dedicated experience in either GHz‑speed RF or GHz‑speed broadband analog design.

• Demonstrated expert proficiency in the Cadence tool suite, specifically Virtuoso schematic, simulation, and custom layout.

• Deep understanding of semiconductor device physics, linearity, noise analysis, and high‑frequency circuit theory.

• Proven track record of taking high‑speed analog blocks from concept to mass production (successful tape‑outs).

Preferred Skills:

• A background in photonic transceivers or optical communication electronics.

• Extensive design experience in TSMC latest technology nodes, such as N5P, N3P, and N2P.

• Experience designing high‑speed data converters.

• Experience designing low‑jitter clocking circuits, including PLLs.

• Proficiency in electromagnetic simulation tools such as EMX or HFSS.

• Experience with frequency domain simulation in Spectre RF.

What We Offer

This is an opportunity to play a pivotal role in an innovative startup redefining the future of AI hardware. Work on game‑changing technology at the intersection of photonics and AI as part of a collaborative, brilliant team. You’ll contribute to a platform that redefines computational performance and accelerates the future of artificial intelligence. Come help us bring this transformative technology to the world.

Benefits

Join a team that invests in your future and your well‑being. At Neurophos, we offer:

• 100% coverage of base health plan premiums for you and your dependents, plus HSA contributions.

• Unlimited PTO. No rigid vacation banks, just a focus on delivery.

• 401(k) matching and stock option opportunities to ensure our success is your success.

• Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance.

• Personalized Benefits. Choose the plans that fit your life and take the cash back for those that don’t.