Pre-Silicon Verification Architect - UVM & Security

Intel; Folsom (CA); Hybrid; USD 164,470 - 232,190; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Retirement plan

Vacation

Job summary

Intel in California, Folsom, is seeking an experienced verification architect who defines and implements verification strategies for pre-silicon designs. You will architect testbenches and develop UVM or formal-based verification approaches, integrating block testbenches into chip-level UVM environments and validating integration.

You will collaborate with analog and digital teams, develop test plans, and enable rigorous post-silicon validation activities while driving security validation

Qualifications

• Bachelor's degree with 10+ years of relevant industry experience, or a Master's degree in a related field with 8+ years of relevant industry experience.
• You must have 8+ years of experience with/in:
• IP/SoC pre-silicon validation and coding using SystemVerilog
• Hardware simulation tools and methodologies (VCS/Verdi)
• IP environment and configuration management tools
• UVM methodology

Responsibilities

• Define, architect, and document verification strategy and methodologies for implementing and verifying pre-silicon design in the most optimal manner
• Architect testbenches and develop Universal Verification Methodology (UVM) or formal-based verification approaches
• Integrate block testbenches in chip-level UVM environments and verify integration
• Develop test strategy, testbench architecture, and test plans for design blocks to conform to specifications
• Enable interaction with analog and digital teams and support post-silicon validation activities
• Collaborate with architecture and design teams to create random test generation plans, run functional simulations to identify gaps in design specifications, and conduct failure analysis, coverage analysis, and closure
• Define and develop the security validation strategy and validation infrastructure to incorporate security tools and methods to improve security coverage

Education

Bachelor's degree with 10+ years of relevant industry experience

Master's degree in a related field with 8+ years of relevant industry experience

Tools

SystemVerilog

VCS/Verdi

IP environment management tools

UVM methodology

Job description

Intel in California, Folsom, is seeking an experienced verification architect who defines and implements verification strategies for pre-silicon designs. You will architect testbenches and develop UVM or formal-based verification approaches, integrating block testbenches into chip-level UVM environments and validating integration.

You will collaborate with analog and digital teams, develop test plans, and enable rigorous post-silicon validation activities while driving security validation