Senior CPU Pre-Silicon Verification Engineer

Intel; Folsom (CA); On-site; USD 141,910 - 269,100; Full time

Job summary

Intel is seeking a CPU Pre-Silicon Verification Engineer in the United States for on-site work in California's Folsom area. You will join the CPU Design Team within SPE to validate core designs before silicon, collaborating with architecture, RTL designers, post-silicon engineers, and platform teams to ensure reliable processor functionality.

The role emphasizes developing validation strategies, coverage-driven approaches, and end-to-end verification across simulation, emulation, and FPGA

Qualifications

• Bachelor's degree in Electrical/Computer Engineering, Computer Science or related field with 5+ years in pre-silicon verification and/or front end.
• Master's Degree in the same field with 3+ years of experience in pre-silicon verification and/or front end.

Responsibilities

• Define, develop, and execute pre-silicon validation plans for Intel CPU core designs.
• Validate CPU functionality, microarchitecture behavior, and system-level feature interactions across simulation, emulation, and FPGA environments.
• Develop validation content, test scenarios, and infrastructure to improve coverage and identify issues early in the product lifecycle.
• Apply coverage-driven validation techniques to ensure comprehensive verification of complex processor designs.
• Review architecture and design changes to assess validation impacts, risks, schedules, and test requirements.

Skills

Programming languages

Pre-silicon verification

Verilog/SystemVerilog

Education

Bachelor's degree (EE/CS)

Master's degree

Tools

VCS

Specman E / UVM

Job description

Intel is seeking a CPU Pre-Silicon Verification Engineer in the United States for on-site work in California's Folsom area. You will join the CPU Design Team within SPE to validate core designs before silicon, collaborating with architecture, RTL designers, post-silicon engineers, and platform teams to ensure reliable processor functionality.

The role emphasizes developing validation strategies, coverage-driven approaches, and end-to-end verification across simulation, emulation, and FPGA