Power Management Architect

Velaura AI, Inc.; Santa Clara (CA); On-site; USD 200,000 - 300,000; Full time

Job summary

Velaura AI, Inc. is seeking a Power Management Architect for our Physical AI SoC to own energy delivery, DVFS, power states, and on-die PMIC interfaces across compute, AI/NPU, memory and I/O. This cross-functional role ties silicon, firmware and platform software to meet tight power and thermal budgets.

You will set power strategy from architecture to tape-out, validate UPF/CPF, and mentor engineers to raise the power-engineering bar across the organization.

Qualifications

• 8+ years in power management, mixed-signal, or SoC architecture.
• Deep expertise in low-power design techniques: DVFS, clock/power gating, retention, and power state management.
• Strong understanding of power delivery networks, PMICs, and thermal constraints.
• Hands-on experience with UPF/CPF and power modeling across the SoC design flow.
• Experience working across silicon design, firmware, and platform software to define and validate power policies.
• Bachelor’s or advanced degree in Electrical/Computer Engineering or related field, or equivalent.
• Excellent written and verbal communication skills, with mentoring experience.

Responsibilities

• Own the SoC power architecture: define power domains, DVFS strategy, power states, and the PDN across the roadmap.
• Define dynamic and static power management techniques including clock/power gating, adaptive voltage scaling, retention, and power state management.
• Establish power and energy budgets and model them across use cases; drive PPA trade-offs with architecture, design, and product teams.
• Architect the on-die power management and control subsystem—PMIC interface, power management controller, sensors, and telemetry.
• Partner with silicon design, firmware, thermal, package, and platform software teams to embed power intent (UPF) into the design flow and validate it.
• Define power and thermal management for sustained real-world operation, including thermal throttling and energy-aware scheduling.
• Establish power architecture standards, modeling methodology, and review practices; mentor engineers.

Skills

Power management

SoC architecture

DVFS

UPF/CPF

PMIC interfaces

Power integrity

Thermal analysis

Cross-functional collaboration

Education

Electrical/Computer Engineering degree

Job description

Role Overview

Velaura is designing the compute silicon that powers robots, autonomous systems, and intelligent machines that operate in the physical world—where energy is scarce, thermal headroom is limited, and every milliwatt affects range, runtime, and performance. As Power Management Architect for our Physical AI System-on-Chip (SoC), you will own the power architecture of our silicon: defining how the chip delivers, distributes, and manages energy across compute, AI/NPU, memory, and I/O so that our platforms hit their performance targets within tight power and thermal budgets.

This is a foundational, cross-cutting role spanning silicon, firmware, platform software, and product teams. You will set Velaura’s power management strategy from the earliest architecture phase through tape-out and production—shaping power delivery, voltage and frequency scaling, low-power states, and the hardware/software control that keeps Physical AI systems efficient in the field.

Responsibilities

• Own the SoC power architecture: define power domains, voltage/frequency (DVFS) strategy, power states, and the power delivery network across Velaura’s Physical AI silicon roadmap.
• Define dynamic and static power management techniques including clock and power gating, adaptive voltage scaling, body biasing, and retention strategies, to maximize performance-per-watt for AI and real-time workloads.
• Establish power and energy budgets and model them across use cases; drive power, performance, and area (PPA) trade-offs with architecture, design, and product teams.
• Architect the on-die power management and control subsystem—PMIC interface, power management controller, sensors, and telemetry—and the firmware/software policies that drive it.
• Partner with silicon design, firmware, thermal, package, and platform software teams to embed power intent (e.g., UPF) into the design flow and validate it through implementation and silicon bring-up.
• Define power and thermal management for sustained real-world operation, including thermal throttling, energy-aware scheduling, and safe operating limits.
• Establish power architecture standards, modeling methodology, and review practices; mentor engineers and raise the power-engineering bar across the organization.

Required Qualifications

• 8+ years in power management, mixed-signal, or SoC architecture, with significant experience defining power architecture for shipping silicon or embedded platforms.
• Deep expertise in low-power design techniques: multiple power domains, DVFS, clock/power gating, adaptive voltage scaling, retention, and power state management.
• Strong understanding of power delivery networks, PMICs, voltage regulation, and the interaction between power, thermal, and package constraints.
• Hands-on experience with power intent and low-power methodology (e.g., UPF/CPF) and with power modeling and analysis across the SoC design flow.
• Experience working across silicon design, firmware, and platform software to define and validate power management policies from architecture through silicon bring-up.
• Bachelor’s or advanced degree in Electrical/Computer Engineering or a related field, or equivalent practical experience.
• Excellent written and verbal communication skills, with a track record of influencing technical direction and mentoring engineers.

Preferred Qualifications

• Experience optimizing power for AI/ML accelerators or NPUs and for real-time or latency-sensitive edge workloads.
• Familiarity with robotics, automotive, mobile, or other power- and thermally-constrained domains, and with battery and energy-storage considerations.
• Experience with energy-aware software/firmware, thermal management, and silicon power characterization and correlation.
• Prior experience at an early-stage or high-growth semiconductor or hardware company, building power architecture and methodology from the ground up.

$200,000 - $300,000 a year

Compensation & Benefits

At Velaura, we believe exceptional talent deserves exceptional rewards. Compensation for this role includes a base salary and very competitive equity compensation, allowing team members to share in the company’s long-term success.

The base pay listed represents a good faith estimate that the Company reasonably expects to pay for this position at the time of hire. Actual compensation will depend on multiple factors, including the candidate’s skills, qualifications, relevant experience, and geographic location.

In addition to base salary and equity compensation, Velaura offers a comprehensive benefits package that may include medical, dental, and vision coverage; paid time off; flexible work arrangements; professional development opportunities; and other benefits designed to support the well-being and growth of our team.

Velaura is committed to pay equity and transparency and regularly benchmarks compensation to ensure we remain competitive in the market.

Why Velaura?

Velaura is building next-generation compute technology for cloud, edge, and Physical AI. Our solutions will enable robots, autonomous systems, drones, and other intelligent machines to operate efficiently in the physical world.

This is an opportunity to help build foundational technology at a time when the industry is undergoing fundamental change. You will work alongside experienced leaders, architects, engineers, and operators who have delivered industry-defining products across mobile, cloud, semiconductor, and AI platforms. If you enjoy solving difficult problems, working across disciplines, and helping shape the future of Physical AI, we would love to hear from you.

Equal Employment Opportunity and Accommodations

Velaura is an Equal Opportunity Employer that is committed to inclusion and diversity. Qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, disability or protected veteran status. We also take affirmative action to offer employment opportunities to minorities, women, individuals with disabilities, and protected veterans.

Velaura is committed to working with qualified individuals with physical or mental disabilities. Applicants who would like to contact us regarding the accessibility of our website or who need special assistance or a reasonable accommodation for any part of the application or hiring process may contact us at: [email protected].

This contact information is for accommodation requests only. Evaluation of requests for reasonable accommodation will be determined on a case-by-case basis.

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.